64b66b code

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The 64b / 66b code is a line code which maps a 64 bit data word into a 66 bit code word. This line code is used in the context of Gigabit Ethernet , such as 10 Gigabit Ethernet, 40 Gigabit Ethernet and 100 Gigabit Ethernet. The 64b / 66b line code is structured completely differently and has different spectral and statistical properties than e.g. B. the 8b10b code .

Like any line code, it is used to spectrally adapt a user data sequence to the physical requirements of the transmission medium such as a line. The type of implementation ensures, in particular, that the code sequence generated is free of direct components , which allows transmission via pulse transformers that do not allow any direct component to pass in the signal. Pulse transformers are used for electrical isolation in the area of ​​the physical Ethernet interface . In addition, the 64b / 66b coding guarantees that the receiver can recover the clock from the code word . This is necessary so that the receiver can recognize the times at which a certain status is transmitted.

functionality

The 66 bits of a code word are introduced by a preamble of 2 bits. The four possible combinations of the preamble each mean:

Preamble 01
The following 64 bits are user data.
Preamble 10
This is immediately followed by a type field with a length of 8 bits with a subsequent 56 bits of control and control information or user data. The meaning depends on the type field. The type field is 8 bits long, but only 16 values ​​and thus functions are permitted; these have a Hamming distance of at least 4 between them.
Preambles 00 and 11
Not allowed. Generate (on the second consecutive occurrence) an error on reception.

The use of 01 or 10 as a valid preamble ensures a signal edge within the preamble. As a result, the symbol clock can be determined on the receiving side by means of a phase locked loop .

The 64-bit user data or 56 bits of control and monitoring data are linked by means of a self-synchronizing scrambler , which means that the data fields are free of constant components only on a long-term average. The scrambler is implemented in the form of a linear feedback shift register . The scrambler approach to 64b / 66b coding is a major difference compared to the table-based line code 8b10b. The codes used in the type field consist of four 0 and 1 bits each , so that no scrambler is required.

The scrambling polynomial is: x 58 + x 39 + 1.

Modifications to the 64b / 66b code

128b / 130b code

The preamble is not followed by 64 bits, but 128 bits. Is used with PCI Express version 3 or higher.

The scrambling polynomial is: x 23 + x 21 + x 16 + x 8 + x 5 + x 2 + 1.

128b / 132b code

The preambles are not 01 and 10, but 0011 and 1100. As with the 128b / 130b code, 128 data bits follow; is used with USB 3.1.

64b / 67b code

The preambles read:

Preamble 001
The following 64 bits are user data.
Preamble 101
The following 64 bits are user data. They are inverted.
Preamble 010
The following 64 bits are control information.
Preamble 110
The following 64 bits are control information. They are inverted.
Preambles x 00 and x 11
Not allowed.

By setting the first bit appropriately, the encoder can actively counteract DC drift and limit the disparity to −33… +33. In the case of a 64b / 66b code, the disparity is not limited even in the statistical mean, which leads to base line drifts that lead to significantly worse transmission properties than e.g. B. those of 8b / 10b codes.

The statistical and spectral properties are much more benevolent than those of the 64b / 66b coding. This code is used in the Interlaken protocol developed by Cisco Systems and Cortina Systems . a. used for communication between Xilinx and Altera FPGAs .

Web links

Individual evidence

  1. ↑ High-Speed ​​I / O Interfaces: Interlaken Protocol FTF-NET-F0154. (PDF; English)