Address decoder

In microelectronics , computer architecture and technical informatics , an address decoder evaluates the bits of a current address in order to select the assigned memory cell or a specific part of the memory (memory module / memory chip).

An address decoder can be technically implemented using a combinational circuit (also a switching network ). Its function can be described by Boolean algebra .

Address decoder selects the memory cell in a memory

An address decoder is a frequently used component in microelectronics that is used to select memory cells in randomly addressable memory modules.

Such a memory cell consists of a fixed number of memory elements or bits . The address decoder is connected to an address bus and reads the address created there. Using a special switching logic, it uses this address to calculate which memory cell is to be accessed. He then selects this cell by selecting it via a special control line. This line is also known as the select line. In dynamic memories (DRAM) there are row and column select lines on the memory matrix, which are controlled by address decoders integrated in the chip.

The logic according to which the memory cell is selected can - depending on the decoder type - be programmable under certain circumstances.

Address decoder selects the appropriate memory module

An address decoder is also used to select the appropriate one from several memory modules or memory chips when a certain address is supplied by the address bus of the processor system.

For this purpose, the memory modules or memory chips have selection inputs, usually referred to as chip select pin (CS) or chip enable pin (CE) pin. Often these inputs have a negative logic function ( CS or CE ), i. H. with an applied logic zero (voltage level low) is selected.

Due to the different combinational logic, the address decoder places the memory modules or chips in the address space of a processor. The memory modules often have a smaller capacity than the address space. In most cases, several modules can be used, even if they have a completely identical structure. It must be ensured that they differ in the address range.

Uniqueness or ambiguity in the assignment of address and memory cell

Access to these modules is usually clearly organized by the address decoder ( injectivity ). Ie an address leads to a memory cell in a module. It does not lead to memory cells in several modules or to several memory cells in one module.

An inversely unambiguous assignment ( uniqueness, bijectivity ) between address and cell in the module is sometimes dispensed with because of the complexity with many input lines in the address decoder. This means that the address is not fully decoded. Several addresses are thus assigned to a memory cell. A memory module is also located in several areas of the address space. This phenomenon is often referred to as mirror addresses or mirrored modules and is also called "mirror". Incomplete decoding can sometimes save hardware effort, but occasionally causes complications for the software.

Example of an 8-bit microprocessor

The often used address width of 16 bits with 8-bit microprocessors corresponds to an address space with 64 k capacity. Addresses are almost always noted in hexadecimal, here - as in the C programming language - the prefix "0x" should be used as a identifier. The address space of the 8-bit microprocessor has the addresses 0x0000 to 0xFFFF.

The address lines are marked with to . The data bus is 8 bits wide. ${\displaystyle A15}$ ${\displaystyle A0}$

In the example, the address space is completely filled with 4 identical RAM chips 16k x 8. The designation 16 k x 8 means 16 k capacity with a word length of 8 bits.

For this purpose, four address decoders are to be implemented, which form their output signals CS _n as combinatorial logic links from the address lines of the address bus.

In this example, the most significant address lines A15 and A14 are to be evaluated there. The remaining 14 address lines can be fed directly to the RAM chips. This means that the following functions can be used for the CS signal of each RAM chip:

Selection for the first RAM chip

${\displaystyle {\overline {CS}}_{0}={A15}\vee {A14}}$

Selection for the second RAM chip

${\displaystyle {\overline {CS}}_{1}={A15}\vee {\overline {A14}}}$

Selection for the third RAM chip

${\displaystyle {\overline {CS}}_{2}={\overline {A15}}\vee {A14}}$

Selection for the fourth RAM chip

${\displaystyle {\overline {CS}}_{3}={\overline {A15}}\vee {\overline {A14}}}$

The above address decoders are used as follows:

The first RAM chip receives the addresses 0x0000 to 0x3FFF,

the second RAM chip has the addresses 0x4000 to 0x7FFF,

the third RAM chip addresses 0x8000 to 0xBFFF and

the fourth RAM chip has the addresses 0xC000 to 0xFFFF.

literature

• Ulrich Tietze, Christoph Schenk, Eberhard Gamm, semiconductor circuit technology , Springer 2002, 12th edition, ISBN 3-540-42849-6

Web links

• Java applet Univ. Hamburg