Advanced high-performance bus

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The Advanced High-performance Bus ( AHB ) is part of the Advanced Microcontroller Bus Architecture ( AMBA ) from ARM Limited (ARM).

The AHB supports:

• several bus masters
• burst transfers
• split transactions
• pipelined operations
• single-cycle bus master handover
• single clock operation
• non- tristate implementation
• large bus widths (64/128 bit).

In this case, AHB replaces the older ASB in new systems, the scope of which is smaller.

A simple transaction on the AHB consists of an address phase and a subsequent data phase, so it only takes two clocks without wait states . Access to the target device is controlled via an arbiter using a Mux (non-tristate) so that only one bus master has access to the bus at a time.

Access to the control bus in the address phase and the data bus in the data phase are assigned independently one after the other so that a bus master can apply the address and control lines in the same clock phase while a second master reads or writes data (pipelined operations ).

literature

• ARM926EJ-S Development Chip Reference Manual

Individual evidence

1. ↑ AHB . ARM info center . Retrieved February 16, 2015.