Embedded Wafer Level Ball Grid Array

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Basic sketch eWLB

Embedded Wafer Level Ball Grid Array ( eWLB ) is a housing design for integrated circuits in which the housing connections are created on a wafer artificially made from chips and potting compound.

development

eWLB is a further development of the wafer-level-ball-grid-array-technology (WLB, also: wafer level package , WLP), which is characterized by the fact that all necessary processing steps for the housing are carried out on the wafer . Compared to classic housing technologies (e.g. ball grid array ), this allows extremely small and flat housings to be manufactured with excellent electrical and thermal properties at particularly low manufacturing costs.

In the case of WLBs that are manufactured on the silicon wafer , all solder contacts must fit on the chip ( fan-in design ). Therefore, only modules with a limited number of contacts can be housed. Related designs are wafer level package and ball grid array.

Micrograph of an eWLB

Manufacturing

In contrast, the eWLB technology allows chips with many contacts to be manufactured. The housing is not manufactured on the silicon wafer, as is the case with classic wafer-level packages, but on an artificial wafer. For this purpose, a wafer that has been processed in the front end is sawn and the individual chips are transferred to a carrier plate. The chips are placed at a greater distance from one another than was the case on the silicon. The gaps and the edge area are now filled with a casting compound. After hardening, an artificial wafer was created which contains a frame made of potting compound (mold frame) around the chips, on which additional solder contacts can be accommodated. After the production of the artificial wafer, the so-called reconstitution, the electrical connections to the soldering connections (connection layers , also called rewiring) are now made using thin-film technology , as is the case with classic wafer-level packages . With this technology, any number of additional solder contacts can be accommodated at the desired spacing on the housing ( fan-out design ). As a result, the wafer-level packaging technology can also be used for new, space-sensitive applications in which the chip area is not sufficient to accommodate the contacts at a realizable distance. The eWLB technology was developed by Infineon . The first building blocks came onto the market in mid-2009 (mobile phone).

Advantages and disadvantages

The advantages are the low costs (housing and test), the minimal housing dimensions in height and width, the excellent electrical and thermal properties and the unlimited number of connections, as well as a high integration potential for multi-chip and stacked components and an emerging housing standard .

The more difficult inspection and repair of the components (visual inspection only possible to a limited extent) and the mechanical stresses between the housing and the circuit board, which are transmitted more to the component than with other housing shapes, have a disadvantage.

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