Gurindar S. Sohi

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Gurindar S. Sohi (* 1960 ) is an Indian - American computer engineer. He is a professor at the University of Wisconsin – Madison .

Sohi received his PhD in electrical engineering and computer science from Edward Davidson in 1985 at the University of Illinois (BLAST: A Machine Architecture for High-Speed ​​List Processing Using Associative Tables) and has been at the University of Wisconsin at Madison since 1985 , where he was from 2004 to 2008 head of the IT faculty.

Sohi dealt with out-of-order execution in microprocessors as early as the 1980s . It was then that he published some influential work that became the basis for later high-performance superscalar commercial microprocessors in the 1990s and beyond. In the early 1990s he propagated the concept of multiskalar processors and thread level speculation (execution of sequential programs in parallel in several processor cores) and in 1997 memory dependence prediction , which is used, for example, in the alpha processor . His work on memory dependencies in superscalar processors was influential in the transition from blocking caches to non-blocking caches. In 1997 he proposed the concept of instruction reuse.

He is an IEEE Fellow and Fellow of the Association for Computing Machinery (ACM), the National Academy of Engineering and, since 2018, the American Academy of Arts and Sciences . In 2011 he received the Eckert-Mauchly Award for the introduction of widespread micro-architecture techniques for parallel computing on instruction level .

1999 received the Maurice Wilkes Award from ACM SIGARCH for fundamental contributions to high-performance processors and parallel computing at instruction level .

Fonts

  • Editor: 25 Years of the International Symposium on Computer Architecture - Selected Papers , ACM 1998
  • Editor with Mark Hill, Norm Jouppi: Readings in Computer Architecture , Morgan Kaufmann Publishers 2000
  • with JR Goodman Memory Systems , The handbook of electrical engineering , CRC Press 1993
  • with James E. Smith The microarchitecture of superscalar processors , Proc. IEEE, December 1995
  • with Andreas Moshovos Micro-Architectural Innovations: Boosting Processor Performance Beyond Technology Scaling , Proceedings of the IEEE, Volume 89, 2001, No. 11

Web links

Individual evidence

  1. ↑ Gurindar S. Sohi in the Mathematics Genealogy Project (English)Template: MathGenealogyProject / Maintenance / id used
  2. ↑ Sohi, p Vajapeyam Instruction Issue Logic for High-Performance, Interruptible Pipelined Processor , 14th annual international symposium on computer architecture (ISCA 87), 1987, pp 27-34, further in IEEE Trans. Computers, March 1990
  3. ^ Scott E. Breach, TN Vijaykumar, Gurindar S. Sohi Multiscalar Processors , ISCA 1995
  4. ↑ Andreas Moshovos, Scott E. Breach, TN Vijaykumar, Gurindar S. Sohi Dynamic speculation and Synchronization of Data Dependences , ISCA 1997
  5. ↑ Manoj Franklin, Sohi High Bandwidth Data Memory Systems for Superscalar Processors , International Conference on Architectural Support for Programming Languages ​​and Operating Systems, ASPLOS 1991
  6. ↑ Sohi, Avinash Sodani Dynamic instruction reuse , 24th ISCA 1997
  7. ↑ Book of Members 1780 – present, Chapter S. (PDF; 1.4 MB) In: American Academy of Arts and Sciences (amacad.org). Accessed October 7, 2018 (English).
  8. ↑ Laudation: For pioneering widely used micro-architectural techniques for instruction-level parallelism
  9. ↑ Laudation: for seminal contributions in the areas of high issue rate processors and instruction level parallelism
personal data
SURNAME Sohi, Gurindar S.
BRIEF DESCRIPTION Indian-American computer engineer
DATE OF BIRTH 1960