Motorola 56001
The Motorola DSP56001 is one of the two first two members of the family of HCMOS digital signal processors (Engl. Digital signal processor , DSP ) from Motorola . The DSP is designed for particularly fast processing of audio signals, fast Fourier transformation , speech recognition, image processing and the like. a. optimized. When 56001 is a fixed-point arithmetic - processor .
The arithmetic logic unit (engl. Arithmetic Logic Unit , ALU ) has four 24-bit input registers, two 48-bit accumulator register and two 8-bit accumulator extension register. At 33 MHz the DSP is able to calculate approx. 16.5 million operations per second (MIPS).
There are four independent bidirectional 24-bit data buses: X data bus (XDB), Y data bus (YDB), program data bus (PDB) and the global data bus (GDB). Some commands of the DSP can combine the XDB and YDB and thus achieve 48-bit precision.
The address buses are each 16 bits wide. An internal memory is assigned to each address bus : X address bus (XAB), Y address bus (YAB) and the program address bus (PAB).
The DSP was used in the Atari Falcon 030 , NeXT computer and various keyboards .
literature
- Motorola: DSP56000 / DSP56001 User's Manual , 2nd Edition, Motorola Ltd., Milton Keynes, 1990.
- Data sheet 56301