Parallel adder with carry bypass

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A parallel adder with carry diversion or carry-skip adder (English carry = carry, to skip = skip) is an adding network , so it is used to add multi-digit binary numbers .

It is an extension of the carry-ripple adder , so it contains a half and several full adders . It has the advantage that the worst-case runtime is improved by counteracting the problem of carry propagation . It is a little slower than the carry-look-ahead adder , but cheaper because fewer gates are required.

For this purpose, the full adders are divided into groups. A fast additional logic determines whether a carry propagates through the entire group, which is the case in the worst case . The additional logic examines whether a carry is received in the group and whether there is at least one 1 in each of the input pairs (a i , b i ) of the group.

In this case, the additional logic reports the carry to the next group, so that the calculation of its result can already begin. No additional logic is required for the last group.

Circuit diagram of a 4-bit carry-skip adder cascaded with a normal 4-bit adder