Full adder

Circuit symbol of a full adder

Circuit symbol of a full adder according to DIN 40900

A full adder (English full adder ) is a switching network , commonly implemented as a digital circuit. It consists of three inputs ( , and ) and two outputs ( and ). With a full adder to three digit can binary numbers add up . Here, the output of which supplies (engl. Sum - sum) the significant digit of the result, the output (engl. Carry (output) the high-order - transfer (output)). The identifiers and suggest a possibility for carry handling in adding networks . ${\displaystyle x}$ ${\displaystyle y}$ ${\displaystyle c_{\mathrm {in} }}$ ${\displaystyle s}$ ${\displaystyle c_{\mathrm {out} }}$ ${\displaystyle s}$ ${\displaystyle c_{\mathrm {out} }}$ ${\displaystyle c_{\mathrm {in} }}$ ${\displaystyle c_{\mathrm {out} }}$

The following truth table shows how a full adder works:

${\displaystyle x}$	${\displaystyle y}$	${\displaystyle c_{\mathrm {in} }}$	${\displaystyle c_{\mathrm {out} }}$	${\displaystyle s}$
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1

This results in the following equations by first building the disjunctive normal form from the truth values ​​of the table and then simplifying it:

${\displaystyle {\begin{aligned}c_{\mathrm {out} }&=\left({\overline {x}}\wedge y\wedge c_{\mathrm {in} }\right)\vee \left(x\wedge {\overline {y}}\wedge c_{\mathrm {in} }\right)\vee \left(x\wedge y\wedge {\overline {c_{\mathrm {in} }}}\right)\vee \left(x\wedge y\wedge c_{\mathrm {in} }\right)\\&=(c_{\mathrm {in} }\wedge (x\oplus y))\vee \left(x\wedge y\right)\end{aligned}}}$

and

${\displaystyle s=x\oplus y\oplus c_{\mathrm {in} }}$

The left figure shows the structure of a full adder using half adders and an OR gate .

Structure of a full adder using two half adders and an OR gate according to DIN 40900

Structure of a full adder with two AND, two XOR and one OR gates according to DIN 40900

The right figure also shows the structure of a full adder, with the half adders each being separated into an AND gate and an exclusive OR gate . It should be noted that in both figures the sum outputs are shown below and the carry outputs of the half adders are shown above. ${\displaystyle s}$ ${\displaystyle c_{\mathrm {out} }}$

If the expression for the full adder is further optimized without slowing down the carry path, further simplifications result:

${\displaystyle {\begin{aligned}I&=x\wedge y\\J&=x\vee y\\c_{out}&=I\vee (x\wedge c_{in})\vee (y\wedge c_{in})\\c_{out}&=I\vee ((x\vee y)\wedge c_{in})\\c_{out}&=I\vee (J\wedge c_{in})\\s&=(x\wedge {\overline {c_{out}}})\vee (y\wedge {\overline {c_{out}}})\vee (c_{in}\wedge {\overline {c_{out}}})\vee (I\wedge c_{in})\\s&=((J\vee c_{in})\wedge {\overline {c_{out}}})\vee (I\wedge c_{in})\end{aligned}}}$

The full adder is used to build adders and multipliers, often with a half adder at the beginning of the carry chain.

literature

• Ulrich Tietze, Christoph Schenk: Semiconductor circuit technology . 12th edition. Springer, 2002, ISBN 3-540-42849-6 .