Parallel data transfer

from Wikipedia, the free encyclopedia
Comparison of parallel and serial data transmission

Parallel data transfers transmit digital data over several lines at the same time. The transmission takes place on several physical lines next to each other or via several channels at the same time in "lock step". If only binary symbols with two possible states are used, one symbol corresponds to one bit that can be transmitted per data path. With n parallel data paths, n bits can be transmitted in parallel in one step.

The parallel transmission over several serial data channels differs fundamentally from a parallel data transmission in the way that there on the lower hardware level all channels are transmitted independently of each other and runtime differences are irrelevant. In the case of parallel transmissions, all data channels work strictly with a common clock regime and are therefore very sensitive to differences in runtime between the channels.


In most cases, parallel interfaces work with 8 or 16 channels. In principle, any other number greater than 1 is possible. Additional lines are required for synchronization. Usually these are cables for data flow control or synchronization (strobe, clock signals ).

A conversion between the parallel and the serial data transmission can take place by means of special assemblies, which are called SerDes .


DDR3 memory modules in which the meandering conductor tracks for the time-of-flight correction of the bus signals can be seen between the print connector and the memory chips

The main disadvantage of parallel data transmission, in addition to the fact that a large number of parallel data transmission paths are required, is the fact that the individual transit times along the parallel lines are not all exactly the same. These inequalities can be caused, for example, by small deviations in the cable lengths and other tolerances in the physical structure of the transmission link. This leads to reception errors or a limitation of the step speed and thus the data transmission rate, particularly at higher walking speeds. For this reason, serial transmission methods are used at higher transmission rates, even if the serial arrangement of the individual symbols results in high symbol rates and large bandwidths .

In this case , an attempt is made to ensure a running time between the individual signals that is as identical as possible by meandering conductor tracks on the circuit boards . The meander shape ensures that all conductor tracks have almost exactly the same length to one another. In addition, delay-locked loops (DLL) are used in the individual circuits, such as the DDR SDRAM chips , which dynamically compensate for runtime differences and thus ensure parallel data transmission at high clock rates.

Examples of parallel data transfers replaced by serial interfaces are the SATA interface, which replaced the ATA / ATAPI interface as well as PCI Express, the PCI , or Fiber Channel as a further development of the parallel SCSI bus variants. Despite a drastic reduction in the transmission lines, the bus systems became faster by a factor of around two.


  • Dietmar Lochmann: Digital communications technology . 2nd Edition. Verlag Technik Berlin, 1997, ISBN 3-341-01184-6 .
  • Roland Hellmann: Computer architecture. Introduction to the structure of modern computers, 2nd edition, de Gruyter Verlag, Berlin / Boston 2016, ISBN 978-3-11-044605-0 .
  • Thomas Flik: Microprocessor technology and computer structures. 7th edition. Springer Verlag, Berlin / Heidelberg 2005, ISBN 3-540-22270-7 .
  • Ekbert Hering, Klaus Bressler, Jürgen Gutekunst: Electronics for engineers and natural scientists . Springer Verlag, Berlin / Heidelberg 2014, ISBN 978-3-642-05499-0 .
  • Hans Liebig: Computer organization. The principles, 3rd edition, Springer Verlag, Berlin / Heidelberg 2003, ISBN 978-3-540-00027-3 .

Individual evidence

  1. DDR Interface Design Implementation. Lattice Semiconductor, 2004, accessed March 4, 2014 .

Web links