Memory address register
The memory address register (SAR) is an important register of a main processor in a Von Neumann computer . Together with the memory data register (SDR) it serves as a fast buffer and reduces the negative effects of the Von Neumann bottleneck .
Most Von Neumann computers are implemented internally as Harvard architectures , which is why a distinction is made between data and address buses . In many systems, both buses are different widths.
The memory address register (abbreviation SAR, English abbreviation MAR for memory address register ) contains the address of the memory word that is to be read or written next. Therefore this register is as wide as the address length.
literature
- Dietmar PF Möller: Computer structures: Basics of technical informatics . Springer-Verlag, Berlin 2013, ISBN 978-3-540-67638-6 .
- K. Mary Reid, Alan Jarvis, Tracey Stump: IT Practitioners . Heinemann Educational Publishers, Oxford 2003, ISBN 0-435-45469-2 (English).
Web links
- William Stallings Computer Organization and Architecture (accessed May 13, 2016)
- Von Neumann calculator (accessed on May 13, 2016)
- Operating Systems (accessed May 13, 2016)