System bus

The term system bus is used to summarize the various data rails ( buses ) via which the CPU in a microcomputer communicates with its environment. As a rule, a distinction is made between three such buses: the data bus , the address bus and the control bus .

System bus types

There are three different types of system bus, which differ in their time behavior. The specification of the time behavior depends on the manufacturer and is also referred to as the system bus protocol . The two main types are synchronous and asynchronous system buses.

The former (synchronous) are clocked so that the transfer of data (in one of the two directions) can only take place with one clock edge .
The second bus type (asynchronous) is not clocked and generally uses a handshake protocol to regulate the transfer of data.
In between there is the third type, which represents an interim solution: the bus is clocked, but the additional use of control lines enables additional waiting cycles to be able to connect slow components to the bus. This type of bus is therefore called semi-synchronous . Most modern microprocessors use a semi-synchronous system bus.

Access to the system bus

Access control using an arbiter, representation of the basic principle

Since many different components want to access the system bus, this access must be controlled. In this context one speaks of bus arbitration control . This control is usually carried out by a special module (e.g. an arbiter or coprocessor). The three signals BREQ (Bus Request), BGRT (Bus Grant) and BGA (Bus Grant Acknowledge) are used for regulation. This procedure is also known as a 3-line handshake.

The procedure is basically as follows. The processor is currently in control of the system bus. For example, he could have created an address on the address bus and now read in the data addressed in this way via the data bus. At the same time, an external component reports to the processor by means of the BREQ signal that it needs access to the system bus. As soon as the processor has finished reading the data via the data bus, it processes the BREQ signal and grants the component access via BGRT. The component responds (possibly optionally) with BGA to the permission, thus informing the processor and other components that it has taken control of the bus. Since external components are generally allowed to access the bus with a higher priority than the processor itself, the processor usually has to relinquish control when there are requests.

But what happens if several BREQ signals are present at the same time? In order to handle such situations, an arbiter module is usually used , which processes the requests, sorts them according to priorities and then forwards them sequentially to the processor. The external components then no longer address the processor directly via BREQ, but have control lines to the arbiter, which regulates everything else.

System bus interface

The interface between the processor and the system bus is known as the system bus interface. It usually contains buffer registers for data and addresses. U. can be organized as a FIFO . The latter is particularly the case when the processor is clocked differently than the system bus in order to enable more efficient buffering.

So-called tristate gates are used for coupling to the bus . In addition to the levels Low and High, these are able to adopt a special high-resistance state at the output in order to decouple the processor from the system bus if other devices are to access it.