Translation lookaside buffer
The term translation buffer or English translation lookaside buffer (TLB, cf. also cache ) denotes a functional unit of memory management of self-reloading memory management units (MMU) .
If virtual memory is used, the associated physical address must be determined for the virtual addresses. With the x86 , the virtual or logical address is usually converted into a physical address in three steps with the help of the segment table and the mostly tree-like organized page table ; other processors ( ARM , PowerPC , MIPS etc.) work similarly. Since these operations are relatively time-consuming, the most recently determined are values for the address of the physical memory page in the TLB cached , thereby re-accesses to addresses in this site do not have to be redetermined consuming but can be removed from this list. The TLB can hold a limited number of these references (usually no more than 1024 entries) and can thus significantly accelerate the execution of memory accesses. This is implemented using associative order registers that allow parallel access. Due to its structure, the TLB per entry is comparatively expensive compared to other volatile memories such as e. B. RAM.
Individual evidence
- ↑ Andrew S. Tanenbaum : Modern Operating Systems. 2nd, revised edition. Pearson Studies, 2003, ISBN 3-8273-7019-1 .