Chips & Technologies Super386
Super386 was a family of processors from Chips & Technologies and was an improved version of the Intel 80386 .
Chips & Technologies integrated two pipelines for instruction execution and, in some versions, even a small L1 cache . The processors thus corresponded more closely to the 80486 generation and were slightly superior to the Intel counterparts in terms of performance. This makes them comparable to the Cx486SLC and Cx486DLC processors from Cyrix . Nevertheless, Chips & Technologies was unable to establish itself on the market and did not develop a successor.
Coprocessor problems
Like all 80386 processors, the Super386 processors can be supplemented with a math coprocessor such as the i387 or a compatible model. There is a bug in the Super386 that affects the communication between the main processor and coprocessor. This is why coprocessors in conjunction with the Super386 only achieve a fraction of their actual performance.
architecture
38600DX and 38605DX
- Max. addressable memory: 4 GB
- Processing width: 32 bits
- Data bus: 32 bit
- Address bus: 32 bit
38600SX and 38605SX
- Max. addressable memory: 16 MB
- Processing width: 32 bits
- Data bus: 16 bit
- Address bus: 24 bit
The external 16-bit data bus enables the use of cheap 80286 chipsets.
Model data
38600SX
The 38600SX is roughly the same as the i386SX and is pin-compatible with it.
- L1 cache: does not exist
- L2 cache: nonexistent
- Design: PGA with 132 pins
- Operating voltage (VCore): 5 V
- Release DATE: 1992
- Manufacturing engineering:
- The size :? at? Transistors
- Clock rates:
- 33 MHz
- 40 MHz
38605SX
The 38605SX roughly corresponds to the i386SX with an additional L1 cache , but is not pin-compatible with it.
- L1 cache: 512 byte data cache
- L2 cache: nonexistent
- Design: PGA with 144 pins
- Operating voltage (VCore): 5 V
- Release DATE: 1992
- Manufacturing engineering:
- The size :? at? Transistors
- Clock rates:
- 33 MHz
- 40 MHz
38600DX
The 38600DX is roughly the same as the i386DX
- L1 cache: does not exist
- L2 cache: nonexistent
- Design: PGA with 132 pins
- Operating voltage (VCore): 5 V
- Release DATE: 1992
- Manufacturing engineering:
- The size :? mm² at? Transistors
- Clock rates:
- 25 MHz
- 33 MHz
- 40 MHz (?)
38605DX
The 38605DX roughly corresponds to the i386DX with an additional L1 cache , but is not pin-compatible with it.
- L1 cache: 512 bytes for instructions
- L2 cache: nonexistent
- Design: PGA with 144 pins
- Operating voltage (VCore): 5 V
- Release DATE: 1992
- Manufacturing engineering:
- The size :? mm² at? Transistors
- Clock rates:
- 33 MHz
- 40 MHz