Dual stress liner

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The English term strain engineering (DSL) referred to in the semiconductor technology , a method for the preparation of strained silicon (engl. Strained silicon ) for p- and n-channel MOSFETs in silicon on insulator technologies (SOI). The process developed by IBM comes through the technology exchange agreement is / was used, among others, by AMD / Globalfoundries and Chartered Semiconductor Manufacturing .

Silicon nitride (Si 3 N 4 ) is deposited over the components after the MOSFET has been manufactured . Depending on the process conditions, this silicon nitride layer has a compressible or relaxing effect on the source and drain regions below . These local stresses have a complementary effect on the channel region between the source and drain regions, that is to say compressed source and drain regions lead to expanded silicon in the channel region and vice versa. Technologically, both types of tension are used: Since the electron mobility increases in relaxed (tensile) silicon, such channel regions are suitable for n-MOSFETs; In contrast, compressible silicon leads to increased hole mobility, which is used in p-MOSFETs.

The advantages of DSL technology lie in its compatibility with the SOI technology propagated by IBM and AMD and in the fact that, in contrast to the strain transfer process used by Intel , the electronic properties of p- and n-channel MOSFETs are equally improved .