Modified-Shared-Invalid Protocol

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The articles MESI , Modified-Shared-Invalid Protocol and MOESI thematically overlap. Help me to better differentiate or merge the articles (→  instructions ) . To do this, take part in the relevant redundancy discussion . Please remove this module only after the redundancy has been completely processed and do not forget to include the relevant entry on the redundancy discussion page{{ Done | 1 = ~~~~}}to mark. Simon04 23:00, Mar 10 2011 (CET)

In Modified, Shared, Invalid ( MSI ) is a protocol for maintaining the cache coherency in memory-coupled multiprocessor systems .

If every processor in such systems has a cache , it must be determined whether one of the caches or the main memory contains the current value of a date . A system that guarantees to get the current value of a date at any time - even if it is in a different cache - is called cache-coherent .

The MSI protocol is mainly used for write invalidate and write back caches and is based on snooping technology.

Within the MSI protocol, each cache block is assigned exactly one of the states Modified, Shared or Invalid. The individual states mean:

  1. Modified: This cache line was changed locally. Further copies in main memory or in the cache of other processors are invalid .
  2. Shared: One or more caches contain this data block. All caches that are in the Shared state have a valid copy.
  3. Invalid: The content of this cache line is out of date or there is still no value in this cache line ("Compulsory Miss").

The central starting point for controlling the state change of the respective cache block is the bus . The individual caches communicate with the main memory via this. Each cache has a cache controller , which z. B. when a date is requested by the processor of the cache, a corresponding command is placed on the bus. In addition, it also monitors commands that are placed on the bus by other cache controllers or other components (e.g. the controller of the main memory). The status changes of the respective cache blocks are carried out according to the own commands and commands that have been listened to. The principle of monitoring transactions and commands on the shared bus is called "snooping".

Transitions between the states

A processor can write (PrWr) or read (PrRd) access to a single address in the memory system. Correspondingly, read and write operations of a processor trigger bus transactions. The following bus transactions exist with the MSI protocol:

  1. Bus-Read (BusRd): The signal is placed on the bus when a processor wants to read the date or the value of a memory block.
  2. Bus-Read-Exclusive (BusRdX): The signal is sent to the bus when a processor wants to overwrite the data in a memory block.
  3. Flush: This signal is generated when only one processor (possibly also the main memory) has the current date of a memory cell in its cache and another processor tries to read or write to the same address of this memory cell. When the Flush signal appears on the bus, the date of the corresponding block is also placed on the bus.

The read and write operations as well as the directly and indirectly generated bus transactions determine the behavior of the state machine , which is defined by the MSI protocol.

The MESI and MOESI protocols are extensions of the MSI protocol .


  • David E. Culler, Jaswinder Pal Singh: Parallel Computer Architecture - A Hardware / Software Approach Morgan Kaufmann, 1999, ISBN 1-55860-343-3