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The articles MESI , Modified-Shared-Invalid Protocol and MOESI thematically overlap. Help me to better differentiate or merge the articles (→  instructions ) . To do this, take part in the relevant redundancy discussion . Please remove this module only after the redundancy has been completely processed and do not forget to include the relevant entry on the redundancy discussion page{{ Done | 1 = ~~~~}}to mark. Simon04 23:00, Mar 10 2011 (CET)

MOESI ( M odified, O wned, E xclusive, S hared, I nvalid ) is a protocol for maintaining cache coherence in memory- coupled multiprocessor systems . It includes all possible states of a cache line that are also known from other protocols. Each cache line is in one of five states (see, p. 165ff):

The MOESI protocol is a complicated variant of the MESI protocol. It avoids writing back modified cache lines when other CPUs want to read them. Instead, the current value is propagated directly between the caches with every change (see Owned state ).

MOESI does not offer any significant advantage over MESI if the connection network between processors and memory controller is a bus . On the other hand, it is an advantage for direct networks, such as AMD Opteron systems. Avoiding the writing back of modified cache lines ensures the relief of the connection network and storage controller. In addition, communication between two or more CPUs in terms of latency and transfer rate can be significantly better than between CPU and main memory. With multi-core CPUs each with its own cache per core, this is usually the case.

In the area of system on a chip , the use of the additional "owned" status can save energy if this means that there is no access to externally connected memory. In the case of the AMBA bus from ARM , the energy required for an external memory access is up to ten times higher than an internal memory transfer between two bus masters, according to the manufacturer. The AMBA bus from version 4 supports the MOESI protocol.

State diagram

Legend for the state diagram

To improve understanding and clarity, the state diagram has been divided into two (for active and passive CPUs). By combining automatons, an equivalent automaton can be generated that combines both diagrams.

conditions description
Read hit Hit when reading locally
Write hit Hit when writing locally
Snoop Hit on Read Hit when reading someone else's
Snoop Hit on Write Hit when writing someone else's
Read Miss Failed to read local
Write Miss Failed to write locally
shared with snoop hits in other caches
not shared without snoop hits in other caches


Modified (more precisely: Modified Exclusive)

The cache owns the only copy of the cache line and has modified it (dirty). If he removes the cache line, he must update the main memory. When a read request comes from another processor, it sends the data from this cache line to it and changes its own state to owned . The state of the cache line of the other processor is set to shared . In the event of a write notification from another processor, it sets its cache line to invalid .

Owned (more precisely: Modified Shared)

The cache has one of several copies of the cache line. It has changed its cache line, but has not yet written it back: There is therefore an outdated (i.e. invalid) value in the main memory. For all other processors that have this cache line, this is in the shared state . The processor is responsible for updating all other caches when writing to this cache line. If another processor sends a read request, the cache sends the current data directly to the requesting party. In the event of a write notification from another processor, it changes to the invalid state . The person who wrote is now in the modified state . For all other caches that have cached this main memory address, the status also becomes invalid and therefore invalid .


The cache has the only copy of the cache line and has not modified it (clean, unmodified). In the case of a read request, it sends the data to the requesting party. The states of both cache lines then change to the Shared state. In the event of a write notification, it invalidates the cache line.


The cache has one of several current copies of the cache line. A cache line in this state may only be read.


The cache line is invalid. If the processor requests it, a cache miss occurs and the data must be fetched from main memory (or another cache). To do this, it sends a request to the memory and to all other processors at the same time. If the cache line is already available in another cache and if it is modified there ( modified or owned ), the data is delivered from there. The data coming from the memory is ignored because it is not up to date. If the cache line was modified in another processor , the status there changes to owned . In any case, the state of the cache line in this cache is set to shared . If the cache line is not modified anywhere, the cache takes the data from memory. Depending on whether the other processors have the cache line in their cache or not, the new cache line is set to the exclusive or shared state . In the case of a read request or a write notification, nothing happens in the invalid state .

See also

Individual evidence

  1. AMD64 Architecture Programmer's Manual Vol 2 'System Programming'
  2. Introduction to AMBA® 4 ACE ™ (PDF; 908 kB)