NMOS logic

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The NMOS logic (from English N-type metal-oxide-semiconductor ) is a semiconductor technology which is used in digital, integrated circuits and is used to implement logic circuits . As a special feature, only so-called n-channel metal-oxide-semiconductor field-effect transistors (n-channel MOSFET) are used.

The NMOS logic was used in the 1970s to the end of the 1980s to implement digital logic circuits such as those found in microprocessors . Except for niche applications, it is no longer used today. It was almost completely replaced by the CMOS logic (lower power dissipation).

construction

Equivalent circuit diagram of the NAND gate with load resistance
NAND gate in NMOS with normally on load transistor T1
NAND gate in NMOS with normally-off load transistor T1
NAND gate in NMOS with normally-off load transistor T1 with U GG  = U th + U DD

The structure of the NMOS logic should be illustrated using a simple NAND gate . The equivalent circuit of a NAND gate with the two inputs A and B and the output Y is shown on the right. The load resistor R has the disadvantage that it takes up a lot of space on integrated circuits (IC). In the first embodiment of NMOS, that load resistor was replaced by a normally-off n-channel FET, which means that only normally-off n-channel MOSFETs are required in the circuit. This had the advantage that fewer process steps are necessary in terms of manufacturing technology in the manufacture of the IC. The two supply voltages required for this are disadvantageous.

An improvement is obtained if the upper load transistor is replaced by a normally on n-channel MOSFET, as shown in the adjacent figure. This also represents the usual switching principle of NMOS logic circuits. This means that only one supply voltage and lower losses can be managed. A disadvantage is the more complicated production, since the normally-on load transistor T1 takes up at least one process step more and more chip area than the switching transistor.

In the case of NMOS, the load transistor acts approximately as a constant current source , so that the cross current is lower than with a load resistance R of constant value . If the self-conducting load transistor T1 is implemented with the low-resistance drain / source diffusion, four masks are sufficient for the production of the NAND gate. If the stage is to be implemented with high resistance, at least five masks are required.

In contrast to the easier to manufacture precursor logic , the PMOS logic, which only works with p-channel MOSFETs, the n-channel MOSFETs used in NMOS have the advantage that only negative charge carriers in the form of electrons occur as charge carriers within the field effect transistor . Electrons have a higher mobility in semiconductors than the positively charged defect electrons ("holes") involved in charge transport in p-channel MOSFETs . The advantage is a higher switching frequency , which can be achieved with NMOS gates compared to comparable PMOS gates.

However, advances in manufacturing processes have made this advantage of NMOS secondary, and CMOS uses a combination of normally-off p-channel and n-channel MOSFETs with significantly lower cross currents than NMOS. Compared to CMOS, NMOS has the following disadvantages:

  • The space requirement is greater, unless high electricity consumption is accepted.
  • In the static operating case, an NMOS gate has a comparatively large cross current with a logical 0 at the output.

An extension of NMOS, with smaller structure sizes and higher packing density, is also known as HMOS .

literature

  • Jerry C. Whitaker: Microelectronics . 2nd Edition. CRC Press, 2005, ISBN 0-8493-3391-1 .
  • M. Glesner et al .: Lecture notes - VLSI Design of Integrated Circuits . Darmstadt University of Technology ( pub.ro [PDF]).
  • Christian Clemen: NMOS inverter . In: Lecture notes: Fundamentals of microelectronics (WS 2000/2001) . Augsburg University of Applied Sciences, 2000 ( PDF ).