NS320xx
The NS320xx were a family of 32-bit processors from National Semiconductor , which were characterized by an extensive instruction set .
development
The first processor of the family presented was the NS16032 (later renamed NS32016 ), this had an external 16-bit data bus and appeared on the market around 1979. The NS32032 followed in 1984 with a completely 32-bit wide data bus and significantly increased performance. Also available was the NS32008 , which was supposed to find a place in the market as an embedded processor with a data bus reduced to 8 bits , but had little success.
With the subsequent NS32332 and NS32532 , the performance was further increased. The planned NS32732 never reached the market. Parts of the development for the NS32732 were then used for specialized processors that were tailored to control laser printers . The NS32000 family has now been completely discontinued.
Type | Introductory year | Clock frequencies | casing | technology | description | |
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NS32008 |
8 MHz 10 MHz |
6 MHz DIP -48 | XMOS / CMOS |
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NS32016 | Late 1970s |
8 MHz 10 MHz |
6 MHz DIP-48 |
|
|
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NS32032 | 1984 |
8 MHz 10 MHz |
6 MHz CLCC-68 | XMOS / CMOS | |
NS32132 |
8 MHz 10 MHz |
6 MHz LCC-68 | XMOS / CMOS |
|
||
NS32332 | 1985 | 10 MHz 12 MHz 15 MHz |
PGA-84 | XMOS / CMOS |
|
|
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NS32532 | 1987 | 20 MHz 25 MHz 30 MHz |
PGA- 175 | 1.25 µm CMOS |
|
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NS32081 | 6 MHz 8 MHz 10 MHz 15 MHz |
DIP-24 |
|
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NS32381 | 15 MHz 20 MHz 25 MHz 30 MHz |
PGA-68 PLCC-68 |
CMOS |
|
Architecture and instruction set
What was remarkable about the NS32xxx was the architecture that was completely based on 32 bits from the start. There were only minimal differences in the instruction set between the different generations of processors. The MMU and FPU functions , which were initially implemented as coprocessors, were integrated into the processor in subsequent chip generations without any noteworthy adjustments to the software being necessary.
The instruction set was very extensive, as were the types of addressing. Various combinations of index and offset registers allowed direct access to complex data structures with a single command. All instructions could use any type of addressing or register for each of their data source or destination addresses, and many instructions could work with two source and one destination address. From the standpoint of symmetry and orthogonality , the NS320xx family instruction set should represent the design pinnacle of what was designed as a CISC CPU.
Web links
- Data book of the NS32000 family (as of 1986) (PDF file; 85.50 MB)
- NS32532 (PDF file; 1.10 MB)
- NS32C032 (PDF file; 803 kB)
- NS32381 (PDF file; 381 kB)