Parity generator
A parity generator is a logic circuit in the field of digital technology that generates an additional control bit (= parity bit) for a data word . In serial transmission , the parity bit is added directly after the data bits of a byte (or word). The parity generator distinguishes between even and odd parity.
Even and odd parity
In the case of even parity, the parity bit has the value 1 precisely when there is an odd number of ones in the data word; in the case of an even number of ones, the parity bit is 0.
In the case of odd parity, the reverse is true: the parity bit has the value 0 precisely when there is an odd number of ones in the data word; if there is an even number of ones, the parity bit is 1.
Realization in hardware
The following circuit of an 8-bit parity generator represents a parity generator with even parity. Such a circuit is used for data and transmission security : A check bit (here: parity bit) is added to the actual data bits , which depends on all input bits, i.e. H. it changes if only one of the input bits changes. If this check bit is fed into a transmission link together with the data bits, an identical circuit can generate a check bit at its end, which in turn is compared with the received check bit.
For circuit implementation of a parity generator logic devices can exclusive-OR gates are used. A downstream inverter at output X can be used to switch the illustrated circuit of the 8-bit parity generator from even parity to odd parity.
Realization in software
In data processing, such check bits are sometimes also generated directly by software (see program code in the figure).
Advanced Security Procedure
Since the check bit in the parity generator does not change if an even number of input bits changes, this method offers only a limited gain in safety. For higher security there are, for example, codes and methods that either have more than one check bit per data word ( Hamming code ) or, for example, use a CRC checksum .