Validation (chip design)

The title of this article is ambiguous. Further meanings are listed under validation .

The validation of the design is an important phase in the chip design . Both the logical function and the time behavior of the design are compared with a given specification.

Validation of the logical function

The description of the logical function of a design is usually done with a hardware description language (similar to a programming language). Complex functions (e.g. addition, multiplication) can be entered and the function can also be simulated with the aid of a special compiler. The logical function can therefore be checked both by simulation and by means of formal verification .

The aim of validation is to achieve all possible internal states of the design and to check all possible transitions to one of the possible successor states. The number of internal states increases with the number of elements to be stored in a design. That number is astronomical in today's designs.

simulation

During the simulation, as many test vectors as possible are generated, which are applied to the inputs of the design. At the same time, the outputs of the design are examined. In order to determine if the design works correctly, it is necessary to have comparative data. A reference model of the design is used for this. The reference model is created according to the same specification regardless of the design. In contrast to design, however, one tries to code the reference model on a level that is as abstract as possible. On the one hand, this enables creation in less time, and on the other hand, it reduces the number of errors. By also executing the test vectors against the reference model, you get data vectors at the outputs. Any difference between the output vectors needs to be investigated and understood, with some of the differences being due not to a design flaw but to a faulty reference model.

Formal verification

As the simulation - as mentioned - can never check all states, one tries to prove with the help of mathematical algorithms that a design is correct. The test vectors are replaced by logical rules. This method also has disadvantages. For one thing, only the rules that have been made are checked and it remains unclear how many rules were not made. On the other hand, the programs that prove the rules have a very high memory and computing time requirement, which is exponentially dependent on the size of the design. Thus, the use of these tools is limited in practice to only parts of the overall design.

Validation of the timing

Special software tools calculate the signal transit times of all possible paths through the design on the basis of the individual gate transit times. The maximum signal runtime must be shorter than the time specified in the specification.