Command cycle

from Wikipedia, the free encyclopedia

The instruction cycle ( English instruction cycle ), as a fetch-execute cycle is known, describes the flow of processing of the machine instruction within a synchronous microprocessor .

Command processing scheme

Schematic structure of a simple CPU (English). The integer unit is responsible for the program flow.

The processing of a machine command takes place according to a fixed multi-level scheme, which is composed of several machine cycles, which usually run at the same time as the CPU clock. Depending on the processor type and the machine instruction set used, there are different versions of the scheme presented below.

1. Load command

First, the instruction must be loaded from the main memory into the processor (English fetch instruction ). To do this, the processor uses the current value of the program counter to determine the position of the instruction in main memory. The relevant instruction is loaded into the memory data register of the processor via the data bus and from there it is transferred to the instruction register (CIR).

2. Decode the command

In this stage (English decode instruction ) the instruction code and the operands are determined. It also determines how the operands must be addressed .

Load command operands

After decoding the instruction, the operands are loaded into the processor (English fetch operands ). The internal steps required for this depend on the addressing used.

3. Execute the command

After loading the required main memory contents into the processor, the command is executed in accordance with the command code . For example, logical commands are processed with the aid of the arithmetic unit .

4. Save the result

The result of the command execution is stored in the main memory (English store results ). If the last command was a jump command, the program counter is set accordingly. Otherwise the program counter receives the address of the next command.

Relationship between command cycle and clock cycle

A machine program consists of a set of machine instructions. During execution, these commands are processed one after the other in one command cycle by the processor. Depending on the complexity of the machine instruction set, each step of the instruction cycle requires several clock cycles . To increase the number of machine commands processed per unit of time, clock frequencies can be increased or a pipeline can be integrated into the processor, for example. With pipelining, the processing of successive machine commands can be parallelized to a certain extent (see also superscalarity ).

example

Structure of a command cycle with the Intel 8085

The diagram on the right shows the command cycle of a typical microcontroller.

  1. Reading of the new instruction from the memory into the instruction register (English: Instruction Register IR ) according to the current address of the command counter (English: Program Counter PC )
  2. Decoding of the command
  3. Increase the content of the PC by +1 (or by the size of the currently loaded command, which is particularly variable with CISC architectures)
  4. Access to the operands, possibly via a new memory read process and an associated address calculation (with indirect addressing)
  5. Performing an operation (e.g. addition)
  6. Results storage

literature

  • Randy H. Katz: Contemporary Logic Design. Benjamin / Cummings, Redwood City CA et al.1994 , ISBN 0-8053-2703-7 .
  • Wolfgang Böge, Wilfried Plaßmann (ed.): Vieweg-Handbuch Elektrotechnik. Basics and applications for electrical engineers. 3rd, improved and supplemented edition. Vieweg, Wiesbaden 2004, ISBN 3-528-24944-7 , p. 595.