Clock gating
Clock gating is a common method used in electronic synchronous digital circuits to selectively switch the clock signal on and off in individual circuit parts and thus reduce the average power consumption of the integrated circuit (IC).
General
Synchronous digital circuits, such as conventional microprocessors , for example, consist of a large number of edge - controlled flip-flops , which are all clocked by a central clock signal, the system clock. As a rule, not all functional units in a microchip are actually needed at every clock edge time - for example, because external events are awaited or certain functional units are not required for a certain task. With clock gating are in appropriate locations in the clock distribution network in the microchip so-called gates, English gates , provided which can stop the clock passing the unneeded functional units.
The background lies in the CMOS technology, in which the digital circuits are manufactured. This technology has a power loss that is heavily dependent on the switching frequency - the higher the clock frequency, the higher the power loss if the clock is always switched on. Clock gating reduces the number of average switching processes in functional units that are not required, which reduces the average switching losses of the entire circuit.
The actual switching process in the clock gate has to be done in such a way that no glitch occurs.
Applications
Microprocessors
Microprocessors usually have one or more "idle" states of different depths, which are activated by special machine commands and put the microprocessor into a power-saving and reduced -power mode by means of clock gating. In addition to software- induced clock gating, microprocessors for mobile use such as the OMAP3 also have their own circuit parts which recognize the current use of parts of the microprocessor, such as the use of the DMA unit, and which are currently not required such as the DMA controller by means of clock Switch off gating temporarily.
Clock division
Clock gating can also be used to reduce the processing speed in a targeted manner without the need for additional clock signals with a lower frequency. The gate circuit is activated periodically. Field programmable gate arrays (FPGAs) have a clock enable input for each edge-controlled flip-flop , which represents a form of simple clock gate. If the clock enable is inactive , the flip-flop ignores the clock signal. If the clock enable input is only switched to active periodically with every second clock edge, this leads to the clock frequency at the flip-flop being halved.
literature
- Stephan Henzler: Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies (Springer Series in Advanced Microelectronics) . 1st edition. Springer Netherlands, 2006, ISBN 978-90-481-7278-8 (reprinted 2010).