Positive emitter-coupled logic
In digital technology , the English term positive emitter-coupled logic (short: PECL, dt. Positive emitter-coupled logic ) denotes a signal standard for representing a two-valued signal as a logic level . The designation is derived from the designation emitter-coupled logic (ECL) and, in contrast to ECL, only needs one positive supply voltage .
Because of the high switching speeds that can be achieved with PECL, it is mainly used to transmit a clock signal . PECL as LVDS a differential signaling is therefore required to transmit a pair of conductors (as _n and _p hereinafter). The two logical states are coded by the sign of the potential difference. The current direction changes accordingly due to the termination required at the end of the line . While PECL is used for 5 V systems, LVPECL ( low-voltage PECL ) is used for the circuit families developed for 3.3 V.
The logic levels for PECL and LVPECL are compiled in the table below.
| Type | V ee | V low | V high | V cc | V cm |
| PECL | GND | 3.4V | 4.2V | 5.0V | |
| LVPECL | GND | 1.6V | 2.4V | 3.3V | 2.0V |
Web links
- http://www.andreas-schwope.de/ASIC_s/Schnittstellen/Buffer_Types/buffer_types.html
- Aaron Reynoso: Interfacing PECL to LVDS. Pericom, August 18, 1999, accessed February 3, 2017 .
- John Goldie: LVDS, CML, ECL - differential interfaces with odd voltages. In: EE Times . January 21, 2003, accessed February 3, 2017 .
Individual evidence
- ↑ Nick Holland: Interfacing Between LVPECL, VML, CML and LVDS Levels. Texas Instruments, accessed April 30, 2014 .