# Logic level

In digital technology, logic levels refer to the electrical voltages mostly used to represent the logic values . However, it can also be about other physical quantities (pressure level in pneumatics , luminous flux in optoelectronics ).

Digital signal (binary)

In the case of digital, usually binary-coded signals , two voltage ranges are allowed, which are called high level (also H level, high , H) or low level (L level, low , L).

## level

In digital technology, information is represented using electrical voltages. As a rule, the information is binary- coded and therefore two voltage levels are required to represent the logic values: the high level, the higher voltage, usually corresponds almost to the operating voltage; the low level as a lower voltage is usually close to 0 volts ( ground reference , GND short of English. ground ). The exact levels vary depending on the type of device used.

To represent the two logic values relatively large level may areas are so real to logic circuits despite tolerances reliably detect the states and associate. The area between the two input level ranges of a logic gate, i.e. between V IL and V IH, is not permitted (prohibited area), the signal voltage cannot be clearly assigned to a logic value there (red in the graphic). A minimum output voltage V OH is therefore guaranteed for the high level on the output side and a minimum input voltage V IH is required on the input side . The output voltage V OH is always greater than the input voltage V IH , the difference V OH  - V IH is called the static signal-to-noise ratio and ensures the operational reliability of the circuits. At low level there is a corresponding maximum output voltage V OL , the maximum input voltage V IL and the static signal-to-noise ratio V IL  -V OL .

Several influences can lead to the reserve of the two permitted areas being exhausted to the forbidden area. For example, the output voltage of a gate is dependent on the load current or the number of gate inputs connected to it. Inductive and capacitive properties of the connections as well as external sources of interference (e.g. through capacitive coupling ) falsify the signal and the components used have manufacturing and temperature-dependent tolerances . Dispersion in cables and fibers can cause flattened signals.

The change between the two logic levels must take place with a minimum edge steepness , the phase of the change is called the signal edge (shown in blue in the graphic).
If the switching edges are not short enough or if a continuously changing (analog) signal is to be converted into a digital one, a Schmitt trigger can be used.

### Default values

common logic levels (all specifications in volts)
entrance output
technology Low (V IL ) High (V IH ) Low (V OL ) High (V OH )
TTL 5 V  ≤ 0.8  ≥ 2.0  ≤ 0.4  ≥ 2.4
CMOS 5 V  ≤ 1.5  ≥ 3.5  ≤ 0.5  ≥ 4.44
LVTTL 3.3V  ≤ 0.8  ≥ 2.0  ≤ 0.4  ≥ 2.4
CMOS 2.5V  ≤ 0.7  ≥ 1.7  ≤ 0.2  ≥ 2.3
CMOS 1.8V  ≤ 0.7  ≥ 1.17  ≤ 0.45  ≥ 1.2
ECL  ≤ −1.4  ≥ −1.2  ?  ?
RS-232 (*)  −15 to −3  +3 to +15  −15 to −5  +5 to +15
HTL 10 ... 30 V  ≤ 0.2 × U B  ≥ 0.6 × U B    ≈ U B
(*) = negative logic, i.e. H. low = 1, high = 0

## Assignment to logic types

### High active and low active

In particular, signals that indicate a state with their level (do not represent a binary digit) are called low -active (active low) or high -active (active high) , depending on whether a low or high level is present of the state. The latter is seldom used, as this is the normal state if there is no name. In principle, negative logic and low -active or positive logic and high -active correspond.

Designations of low- active signals are usually marked with an overline. Alternatively, asterisks or slashes are placed in front or behind. The spellings BSP, *BSPand /BSPshould all indicate that the signal BSP is low-active.

This designation as low- active or high- active depends on the designation, for example the designation of a control input with / ena (from enable = activation when low ) would be equivalent to the name dis (from disable = inactive when high ).

### Positive and negative logic

In the so-called positive logic encodes the high level to a binary 1 and the low level of the binary value 0, negative logic is high level, the 0 and the low level 1 represents.

Certain applications use negative logic. This is the case, for example, with the V.24 or RS-232 interface, and with the IEC-625 interface, the entire handshake is implemented as negative logic.

Positive and negative logic are just a notation in digital technology. If a signal is reinterpreted in negative logic instead of positive logic (or vice versa), this corresponds to a negation at all affected inputs and outputs. For example, if an AND gate for positive logic, with inputs A, B and output Y and the function

${\ displaystyle Y = A \ wedge B}$

is used in an environment with negative logic, results from negating A, B and Y and then transforming it with the laws of De Morgan

${\ displaystyle Y = {\ overline {{\ overline {A}} \ wedge {\ overline {B}}}} = {\ overline {\ overline {A}}} \ vee {\ overline {\ overline {B} }} = A \ vee B}$

An AND gate for positive logic thus acts as an OR gate for negative logic. (See also: Wired-AND , Wired-OR )

## literature

• JEDEC / EIA : JESD8-C.01: Interface Standard for Nominal 3 V / 3.3 V Supply Digital Integrated Circuits . EIA, o. O. 2007. (English, standard for LVTTL 3.3V)
• JEDEC / EIA: JESD8-5A.01: 2.5V ± 0.2V (Normal Range), and 1.8V to 2.7V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit . EIA, o. O. 2007. (English, standard for CMOS 2.5V)
• JEDEC / EIA: JESD8-7A: 1.8V ± 0.15V (Normal Range), and 1.2V - 1.95V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit . EIA, o. O. 2006. (English, standard for CMOS 1.8V)

1. a b EIA-232