1-out-of-n decoder
In monolithic integrated circuits , NAND gates are often used instead of AND gates .
A 1-out-of-n decoder is a circuit with n outputs and log 2 ( n ) inputs. In practice, however, the number of inputs must be rounded up to the nearest whole number if log 2 ( n ) is not a whole number. The output addressed in each case goes to high when the binary number A at the input corresponds to the number J of the relevant output y J. The other outputs are then not activated and remain at low.
| value | entrance | output | ||||||
|---|---|---|---|---|---|---|---|---|
| A = J | a 1 | a 0 | y 3 | y 2 | y 1 | y 0 | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | ||
| 2 | 1 | 0 | 0 | 1 | 0 | 0 | ||
| 3 | 1 | 1 | 1 | 0 | 0 | 0 | ||
This circuit function is implemented directly in commercially available components. Common IC modules are the TTL module 74LS42 and the CMOS module 4028 , each with ten outputs.
This logic function is also used in complex integrated logic components. For example, this function is used as a row decoder and column decoder for addressing rows and columns in memory components ( RAM , ROM , EEPROM , ...). In addition, this logic function can also be implemented in a programmable logic circuit (PLD) or an FPGA component or an ASIC component.