BITBUS
BITBUS ( IEEE 1118 ) is an open and non- proprietary fieldbus . BITBUS was originally specified by Intel in 1984 and adopted as an international standard in 1991 under the name IEEE 1118 . It is based on two common standards. The RS485 interface is used as a physical connection between the individual devices. On the software side, Synchronous Data Link Control (SDLC) is used.
The following properties are assigned to BITBUS:
- A low total cost of ownership (TCO)
- reliability
- Deterministic behavior
- The real-time control is the field delegated
- Very good distance to transmission speed ratio
- Support on many operating systems
Link length and speed
Depending on the length of the bus, different data transmission speeds can be implemented. With a bus length of 300 meters, a maximum speed of 375 kBit / s is possible. If the fieldbus route extends over a distance of 1200 meters, transfer rates of 62.5 kBit / s are still possible.
cabling
The wiring is carried out according to the specifications of the RS485 specification . However, this does not determine the pin assignment , which has to be made as specified in the pin assignment table .
| Pin code | Function / remark |
|---|---|
| 1 | - not used - |
| 2 | - not used - |
| 3 | Data B (-) |
| 4th | RTS B (-), optional |
| 5 | Signal ground |
| 6th | - not used - |
| 7th | - not used - |
| 8th | Data A (+) |
| 9 | RTS A (+), optional |
There are twisted pair cable used to connect the individual devices. The lines Data A and Data B form a twisted pair of wires and the optional RTS A and RTS B connections . However, these are only required in segments that are beyond a repeater , if one is used. The cables are shielded by signal ground.
A 9-pin D-Sub connector is used as the connector.
Data transfer
A maximum of 248 bytes of user data can be transmitted per data packet .
Bit coding
BITBUS distinguishes between two data coding techniques , "synchronous mode" and "self clock mode".
In "synchronous mode", another pair of lines is required to transmit the synchronous pulse.
In "Self Clock Mode", the bits are not transmitted according to the NRZ standard , but rather according to NRZI with "Zero Bit Insertion". Therefore most repeaters or fiber optic converters cannot be used. (Source: (c) Intel Corporation 1988, THE BITBUS (TM) INTERCONNECT SERIAL CONTROL BUS SPECIFICATION, Order Number: 280645-001)
Bus topology
Within the bus topology , a maximum of 28 participants can be connected to one another in a bus segment. When using repeaters , the number of connected devices can be increased up to 250. If more than two repeaters are connected in series, the data rate is only 62.5 kBit / s. If this speed is used, up to ten repeaters can be connected in series. Each repeater can drive a bus segment with a length of 300 m or 1200 m, depending on the desired transmission speed ( see above ). A repeater loads the bus like an ordinary participant.
The bus must be provided with a 120 Ohm terminating resistor at both ends of the line .
addressing
The address space for the BITBUS ranges from 0 to 255 ( hexadecimal : 0x00 to 0xff). Each participant is assigned its own address in the form of a number from 1 to 249. The addresses 0 and 250 to 255 are reserved and must not be assigned to any bus user. In the old BITBUS specification, 255 addresses the local network card . In the newer IEEE 1118 standard, 255 is used as the broadcast address.
Data Link Protocol
The data link protocol used in BITBUS Interconnect is a subset of the SDLC standard developed by IBM , but does not claim to be fully SDLC compatible. Based on this, the specification defines the connection of a master with several slaves on the bus topology. The data link protocol is essentially responsible for the framing of messages and their control during transport. This is achieved by defining a system status, a uniform frame format, control fields and bus operations.
System status
Since the system that has been set up is a hierarchical system, the system status is defined from the point of view of the master. The hierarchical structure can consist of a simple, flat or a complex, multi-level hierarchy. The accounts of the system can consist not only of simple but also of intelligent nodes, which are able to realize different operating speeds, especially in multi-level operation.
State of the master
The master has full knowledge and control of its internal state. However, since the functionality of the slaves does not depend on its status, its status is never transmitted and remains undefined.
State of the slave
In contrast, however, the internal state of a slave is essential for the correct functioning of the master. Because precise detection is not always given by the physical separation of the nodes, the standard defines a status transfer mechanism that enables the master to keep records of the internal status of each slave. The recorded status is assumed to be given for the next communication with a slave. If there is a discrepancy between the assumed and the actual state of the contacted slave, a sequence of actions takes effect, which leads to a resynchronization of the two communication partners.
The status of a slave consists of two pieces of information:
Slave device mode
The "Slave Device Mode" describes the operating mode of the slave. The operating modes "Normal Disconnect Mode" and "Normal Response Mode" are defined in the standard. The slave is in one of the two modes at all times.
A device is in "Normal Disconnect Mode (NDM)" if a local reset or an unrecoverable error has occurred during message exchange. In this state, the slave waits for a specific signal from the master, which allows it to switch to normal response mode. There is no further exchange of messages with the master in this state.
A device is in "Normal Response Mode (NRM)" if the slave in the NDM has received the specific signal for the change of state. After the transition to the NRM, the status is synchronized with the master node. All counters are initialized with 0. The exchange of messages with the master is permitted in this state, provided that there is synchronization.
Sequence counter
A sequence counter is used in the NRM to avoid packet loss and to detect duplicates. Each slave internally manages a tuple (N r , N s ), consisting of the count N r of the next expected message and the count N s of the message for which confirmation is still expected. The master also saves such a tuple for each slave. It represents the last known state of the slave for the master. Every message that is exchanged via BITBUS Interconnect contains the tuple so that a comparison can take place when it is received. There are three possible scenarios:
- Correct sequencing
- Recoverable sequencing error
- Unrecoverable sequencing error
In the event of an irrecoverable sequencing error, the slave must be re-synchronized with the master and goes over to the NDM.
Web links
- Homepage of the BITBUS European Users Group eV (BEUG) (English)
- BITBUS basics