DLX processor

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The DLX microprocessor (pronunciation: deluxe) is a hypothetical processor architecture developed by John L. Hennessy and David A. Patterson (the original designers of the MIPS and Berkeley RISC architecture). It was introduced in the book Computer Architecture: A Quantitative Approach, which they wrote together . The DLX processor is controlled with a RISC instruction set and has 32 registers. There are DLX simulators that graphically display the different pipeline stages and interpret assembler commands. These are used at some universities in lectures on hardware-level programming.

pipeline

The DLX processor pipeline consists of five stages:

  1. Instruction Fetch (IF): Loading the instruction into the instruction buffer, increasing the instruction counter.
  2. Instruction Decode (ID): Generation of the processor-internal control signals, provision of the operands from the registers.
  3. Execute (EX): ALU executes an operation, calculation of the effective address for load / save commands.
  4. Memory Access (MEM or MA): Execution of memory access for load / store commands. Other commands pass through this phase passively.
  5. Write Back (WB): Writing the operation result into a register . Commands with no result pass through this phase passively.

The design of the DLX pipeline prevents the occurrence of write-to-read (write after read) , and write-after-write conflicts (write after write) . Read-to-write conflicts (read after write) are not prevented.

Register meanings

  • R0 zero; immutable
  • R1 reserved for the assembler
  • R2-R3 function return values
  • R4-R7 function parameters
  • R8-R15 any
  • R16-R23 register variables
  • R24-R25 any
  • R26-R27 reserved for the operating system
  • R28 Global pointer
  • R29 stack pointer
  • R30 register variable
  • R31 return address

Command formats

A DLX command is always 32 bits long. The different command formats define the division of the 32-bit command into fields. In all three formats, the first 6 bits are always the opcode .

I format (immediate)

Commands of this format are load / store instructions, arithmetic commands or conditional / unconditional jumps. The instruction consists of a source register rs1 and a destination register rd. In addition, 16 bits are provided for the immediate value, which are used depending on the command type.

Command format of the DLX architecture, Type I.

Example commands: LW, SW, JALR

R format (register)

This format is used to perform operations on registers. The source registers rs1 and rs2 are executed with the register ALU operation func, and the result is stored in the rd register.

Command format of the DLX architecture, type R

Example command: SLT, ADD, SUB

J format (Jump)

Instructions in this format are jump instructions. The (distance) is simply added to the command counter .

Command format of the DLX architecture, type J

Example commands: J, JAL

Instruction set

Extract from the DLX command set without floating point commands : 

Instruction                       Instruction meaning
LB / LH / LW         R1,val(R2)   Load byte / load half word / load word
LBU / LHU            R1,val(R2)   Load byte unsigned / load half word unsigned
SB / SH / SW         val(R2),R1   Store byte / store half word / store word
LHI                  R1,#val      Load high immediate
ADD / SUB            R1,R2,R3     Add / subtract
ADDU / SUBU          R1,R2,R3     Add unsigned / subtract unsigned
ADDI / SUBI          R1,R2,#val   Add immediate / subtract immediate
ADDUI / SUBUI        R1,R2,#val   Add immediate unsigned / subtract immediate unsigned
AND / OR / XOR       R1,R2,R3     And / or / exclusive or
ANDI / ORI / XORI    R1,R2,#val   And immediate / or immediate / exclusive or immediate
SLL / SRL / SRA      R1,R2,R3     Shift left logical / shift right logical / shift right arithmetic
SLLI / SRLI / SRAI   R1,R2,#val   Shift- left log. / right log. / right arithmetic -immediate
SLT / SLE / SEQ      R1,R2,R3     Set- less than / less or equal than / equal
SLTI / SLEI / SEQI   R1,R2,#val   Set- less than / less or equal than / equal -immediate
SGT / SGE / SNE      R1,R2,R3     Set- greater than / greater equal than / not equal
SGTI / SGEI / SNEI   R1,R2,#val   Set- greater than / greater equal / not equal -immediate
BEQZ / BNEZ          R4,name      Branch equal zero / branch not equal zero
J                    name         Jump
JR                   R5           Jump register
JAL                  name         Jump and link (save return address in R31)
JALR                 R5           Jump and link register (save return address in R31)
val:  16 Bit Wert als Adress-Offset oder Immediate-Wert
name: 16 oder 26 Bit Adress-Distanz

literature

  • Philip Sailer, David Kaeli: The DLX Instruction Set Architecture Handbook. , Morgan Kaufmann, San Francisco 1996, ISBN 1-55860-371-9 . (engl.)
  • John Hennessy, David Patterson: Computer Architecture. A quantitative approach. , 3rd edition, Morgan Kaufmann, San Francisco 2003, ISBN 1-55860-724-2 (English)
  • Uwe Brinkschulte, Theo Ungerer: Microcontrollers and microprocessors , Springer-Verlag, Berlin 2007, ISBN 978-3-540-46801-1 , page 49.

Web links

Individual evidence

  1. ↑ Jurij Silc, Borut Robic, Theo Ungere: Processor Architecture: From Dataflow to Superscalar and Beyond . Ed .: Springer Science & Business Media. 2012, ISBN 3-642-58589-2 , pp. 19 .