Data path
A data path is a collection of arithmetic units , such as B. ALU or multipliers that perform data processing operations , registers and buses . Together with the control unit , it forms the CPU .
Recently, there has been an increase in research in the area of reconfigurable data paths - these are data paths that could be repurposed during runtime using FPGA . These designs can potentially result in more efficient calculations and significant energy savings.
Functional blocks of a data path
In computer processors, the data path consists of the following functional blocks or variations of these:
- The instruction register stores the current instruction in order to execute it.
- The instruction counter (PC for short) stores the address of the next instruction in order to then load it.
- The memory address register (SAR for short) is a register that stores the memory address whose data is fetched or overwritten by the CPU.
- The memory data register (SDR for short) is a register of a computer control unit that contains the data that has been stored in the main memory or fetched from there.
There are also two registers within the processor that enable communication between the processor and memory - or in principle help with the memory operations of the register.
Single bus structure of a data path
The first and therefore most important connection element for all registers within the processor is the system bus . This bus is the processor bus and should not be confused with the external bus that connects various memory chips and input and output devices to the processor.
This external bus is connected to the internal system bus via the SAR and SDR registers. The data lines from the external bus are connected to the SDR and the address lines from the external bus are connected to the SAR. The SDR is a bidirectional register; H. it can send and receive data on internal and external buses. The SAR is a unidirectional register; it receives its input from the internal bus and presents its output to the external bus.
The ALU is used to perform arithmetic and logical operations on the data stored in the various registers. It's the heart of a microprocessor. The multiplexer (MUX for short) is provided to select either the constant value 4 or the X register. The constant value 4 is selected when an instruction has been completed and the program counter (PC) is incremented. {As mentioned earlier: (PC ← (PC) +4)}. The "instruction decoder and control logic" block decodes and transfers the current instruction to the IR register.
The processor uses all of these blocks together to perform various primary operations; Examples are:
- Inter-register data transfer
- Arithmetic or logical operations
- Retrieve data from memory
- Write data to memory
Examples
Now let's look at addition as an arithmetic operation and fetching data from memory in detail.
Example 1) Arithmetic addition: The contents of reg1 and reg2 are added together and stored in reg3.
Sequence of operations:
- reg1 out , X in
- reg2 out , choose X, ADDITION, Y in
- Y out , reg3 in
The control signals written in one line are executed in one clock cycle. All other signals remain unaffected. In the first step, the content of register 1 is written to register X through the bus. In the second step, the content of register2 is placed on the bus and the MUX selects input X as the content of reg1, which is stored in register X. The ALU then adds the content of register X and reg2 and saves the result of the addition in the special temporary register Y. In the final step, the result that is in register Y is sent to register reg3 via the internal processor bus and stored there. Only one register can send its data over the bus per step, so steps 2 and 3 cannot be combined.
Example 2) Retrieving data in memory: In order to retrieve data from the memory, the processor must know the address at which the required data is stored. The data that is in a certain memory location can either be an instruction of a program or an operand of a certain executable instruction.
The sequence of operations for this is as follows:
- reg1 out , MAR in ,, READM
- MDR inEX , WMC
- MDR out , reg2 in,
The English abbreviations MAR for the memory address register (SAR) and MDR for the memory data register (SDR) were used. The control signal WMC stands for English wait for memory operation to complete , German 'Wait until the memory operation is completed'. Usually the addressed device on the memory bus is slower than the microprocessor. The microprocessor therefore has to wait until the addressed device has processed its command. This indication that the memory operation has been completed is communicated to the processor via the control signal WMC.
The memory data register MDR is a bidirectional register; it is connected to both buses (internal and external). Therefore the signal MDR is indexed as EX - the abbreviation stands for external bus. The signal implies that data has been shifted from the external memory bus into the memory data register MDR. The remaining control signals are self-explanatory and can be understood as in example 1.
A fully executed instruction
Now let's put the original operations together to see how a full instruction is executed.
If we pull z. B. consider the following instruction:
- ADD (reg3), reg1.
This instruction adds the data from the shown storage location Register3 to the content of Register1.
The sequence of control signals for the above complete instruction is as follows:
- PCount out , MAR in , READM, Choose4, ADDITION, Y in
- Y out , PC in , X in , WMC
- MDR out , IReg in
- reg3 out , MAR in , READM
- reg1 out , X in , WMC
- MDR out , ChooseX, ADDITION, Y in
- Y out , reg1 in , STOP
The first three of the steps described are common to all microprocessor instructions . These form the phase “Get the command” mentioned earlier. Then the instruction is loaded into the instruction register. The "instruction decoding and control circuit" then decodes the instructions and then switches on all control signals that are required for steps 4 to 7. Steps 4 through 7 represent the "execution based on command fetch" phase.
The content of register 3 is copied into the memory address register MAR and in step 4, which transfers the address of the desired memory location and the READM instruction is executed. The content of register 1 is transferred to register X via the bus. As soon as the READM command is completed, the data is made available from the desired storage location in the MDR storage data register. The multiplexer value, which is stored in Y, is sent via the bus to register 1 in the seventh step.
The content of the updated program counter is copied into register X in the second step. Although it is not needed for the above mentioned program, the updated value of the PC is generally always stored in the register X in the case of Branched instructions (English branched instructions ), the branch target address (English target branch address ) into account.
Multi-bus structure of a data path
The internal structure of a processor as described above is a single bus structure. This is useful for theoretical considerations. In practice, however, such single bus microprocessors cannot be implemented. Their structure would result in very extensive control signal sequences. To reduce the number of steps required for an instruction, a multi-bus structure is used.
Individual evidence
- ↑ a b The Essentials of Computer Organization and Architecture by Null & Lobur, 4e, pg 216 "All computers have a CPU that can be divided into two pieces. The first is the datapath, which is a network of storage units (registers) and arithmetic and logic units ... connected by buses ... where the timing is controlled by clocks. "
- ↑ JR Hauser and J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor ( page no longer available , search in web archives ) Info: The link was automatically marked as defective. Please check the link according to the instructions and then remove this notice. , FCCM '97, 1997, pp. 12-21.
- ^ Computer Organization by Hamacher, Zaky, vranesic.
