Dual damascene process

In semiconductor technology, the dual damascene process describes a group of process sequences for the joint ("dual") production of conductor track levels and vertical interconnections (so-called vias). The processes represent a further development of the simple Damascene process and are used in the production of the metallization levels of integrated circuits ( microchips ) using copper technology.

The name "Damascene" comes from an ancient decoration technique, inlaidation (also called damascene, English damascening ), in which a material is inserted into previously made depressions.

background

At the beginning of the 2000s, some semiconductor manufacturers switched the conductor track material for their products from aluminum to copper, which is more electrically conductive . Since layers made of copper, unlike aluminum, cannot be structured using dry etching processes , this change also made it necessary to switch to a different production principle. This led to the introduction of the galvanic deposition of copper in previously manufactured depressions in the dielectric interlayers, the damascene process and its further development, the dual damascene process. The crucial difference between these two process sequences is that in the dual damascene process the vias (from English vertical interconnect access , contact connections between two metallization levels) and the metallization level above are filled with copper in one process step. Compared to two successive Damascene steps, with which the same structure could be produced, a copper deposition, including diffusion barrier and seed layer deposition, as well as a copper CMP step, in which the copper protruding after the galvanic deposition is leveled , is achieved in this way , saved. The reduced number of process steps saves material, time and thus costs.

Basic principle

The reduction of the necessary metal deposition and CMP steps is achieved in that the structures of the via and one conductor level are manufactured before the metal deposition and are filled with metal together. Analogous to the damascene process, the dual damascene process can also be roughly divided into three larger process sections: 1. the deposition of the dielectric, 2. the structuring of the dielectric, and 3. the deposition of the conductor track material. In contrast to the Damascene process, however, a simple dielectric layer is not deposited and structured, but a complex dielectric layer stack. In addition, the structuring of the two partial layers is (significantly) more complex than with a single layer.

The principle of the dual-damascene process is most easily understood if the interlevel dielectric ( English inter-level dieletric , ILD, and inter-metal dielectric , IMD) is assumed for the interconnects and vias as a dielectric stack of three layers. The upper IMD layer will later contain the horizontal conductor tracks of this metallization level. In contrast, the vertical electrical connections (vias) between the current and the previous metallization level are made in the lower ILD layer.

Both layers are usually about the same thickness. The material used is usually silicon dioxide or a low-k dielectric . Typical layer thicknesses are in the range 300–700 nm , depending on the technology node . The ILD is separated from the IMD by a thin intermediate layer. This intermediate layer serves as an etch stop during manufacture. Therefore, a material is selected here that has a significantly lower etching rate than IMD for the etching processes used. In a conventional example process with silicon oxide as the ILD / IMD, a silicon nitride layer that is approximately 30 nm thick can be used for this purpose .

The three layers are usually deposited in direct succession. An exception is the self-adjusting dual damascene process, which deviates from the basic principle in this production phase. In this variant, the etch stop layer is structured before the IMD dielectric is deposited (see self-aligning dual damascene process ).

In the second section of the process sequence, the conductor track and via structures are etched into the deposited dielectric layer stack. To do this, various sequences of photolithographic structuring and dry etching are used (see section Variants ).

As with the Damascene process, the final step is the deposition of the conductor track material (mostly copper) in the etched structures of the layer stack. Since copper diffuses very easily into the dielectric and silicon and interferes with the electrical function there, a copper diffusion barrier must be deposited on the side and bottom surfaces of the trenches and vias before the trenches and vias are filled. It is applied as a conformal layer over the entire wafer and removed in the unneeded areas on the top of the IMD dielectric after the copper CMP. The barrier layer reduces the via diameter. Since this reduction can usually not be compensated by larger vias, the electrical resistance of the via increases. In order to minimize this effect, barrier layers or layer systems made of electrically conductive materials are used, for example binary compounds such as tantalum or titanium nitride . After the deposition of the diffusion barrier, the trenches and vias are filled with the conductor track metal, which is usually electrodeposited. The structures become overcrowded. The excess metal on the top of the layer stack is then first leveled by chemical-mechanical planarization (CMP) and then removed down to the diffusion barrier or down to the dielectric, so that a surface that is as flat as possible is obtained.

In order to prevent corrosion of the copper conductor tracks, an encapsulation layer is deposited after the CMP. Since it must be ensured in subsequent process steps that copper does not diffuse into the layers above, the encapsulation layer must also represent a copper barrier. In this case, however, the electrically conductive barrier system used for the side walls cannot be used, because a conductive layer present on the entire wafer would short-circuit all lines. That is why a dielectric material such as silicon nitride (Si ₃ N ₄ ), silicon carbide (SiC) or silicon carbonitride (SiCN) is used.

Structuring variants

The above-described requirements for the joint filling of vias and conductor track trenches can be provided in various ways. The three most common basic variants of the dual damascene process, which differ in the order of the necessary photolithography steps and of which there are further process variations, are:

TFVL dual damascene process (from Trench First, Via Last , German "Trench first, Via last")
VFTL dual damascene process (from Via First, Trench Last , German "Via first, trench last")
self-aligned dual-damascene , German "self-adjusting dual damascene process"

Nowadays, however, other technically demanding variants are in use in industry, but these can reduce the costs per conductor track level, for example because fewer lithography steps and / or less time are required or the electrical properties are improved. These include above all variants that are based only on a (thicker) dielectric layer. In this case, for example, parasitic capacitances are reduced, since an intermediate layer always increases the dielectric constant of the overall stack and thus its electrical capacitance. In addition, numerous other process sequences (such as the dual damascene process with a metallic hard mask or with multi-layer photoresists) have been developed in order to meet the increased requirements for photolithographic structuring and the integration of new materials.

TFVL dual damascene process

TFVL dual damascene process (basic scheme)

The TFVL dual damascene process was the first implemented dual damascene process variant. As the name describes this variant, the etching of the trenches are (here English trench ) in the interconnect layer before the etching of the vias in the underlying ILD layer. The deposition of the ILD layer stack is followed by the deposition of a photoresist layer and its photolithographic structuring with the pattern of the trench structures. The photoresist mask serves as an etching mask in the subsequent dry etching process of the dielectric. The etching process ends at the dielectric etch stop layer that was applied between the dielectric of the conductor track level and the via level below.

After the trenches have been etched, the first photoresist layer is removed again and a second photoresist layer with the structure pattern of the vias is applied. This is followed by a second etching step in which the etch stop layer is first opened and then the via is etched into the ILD layer. The photoresist layer protects the other areas of the wafer surface, including the side walls of the trench structure. After the vias have been etched, the photoresist residues are removed and the conductor track metal is deposited (if necessary with a barrier layer system).

The main disadvantage of the TFVL approach is that during the photolithographic structuring of the vias, a photoresist layer as homogeneous as possible has to be deposited, both on top of the ILD layer stack and in the trench structures. For this, the liquid applied photoresist must be relatively thick. However, since the resolution of small structures is more difficult to achieve in thick photoresist layers than in thinner photoresist layers, it is more difficult to transfer the TFVL process to smaller technology nodes. The via structuring step therefore requires a relatively demanding photolithography, which is why the via first technique is more widespread in industrial production.

VFTL dual damascene process

VFTL dual damascene process (basic scheme)

With the via-first approach, the position of the via structures is defined in front of the conductor track structures. The process sequence essentially corresponds to that of the trench-first approach, with the difference that the structuring of the via and conductor track levels have been swapped. This means that after the dielectric layer stack (ILD, stop layer and IMD) has been deposited, a photoresist mask is produced with the structure pattern of the vias and the entire layer stack is etched with this pattern (with the exception of the diffusion barrier under the via level). After removing the (via) photoresist mask, the second photoresist mask is produced with the structures of the trenches and the structures are etched into the upper dielectric layer (IMD) until the etch stop layer is reached. The barrier layer on the bottom of the vias is protected from the etching attack by photoresist or a BARC material (BARC = bottom antireflective coating , in other words , "lower anti-reflective layer "). Alternatively, a highly selective etching process that does not attack the barrier material is also used. After the trenches have been etched, the photoresist residues are again removed and the conductor track metal is deposited (if necessary with a barrier layer system).

The via-first approach is currently the most widely used variant for the production of dual damascene connections.

Self-adjusting dual damascene process

Self-adjusting dual damascene process (basic scheme)

As already mentioned, the self-adjusting dual damascene process deviates somewhat from the basic principle described above. In contrast to the trench-first and via-first approaches, in this variant, after the deposition of the dielectric of the via level (ILD) and the etch stop layer, the upper dielectric (IMD) is not deposited immediately, but the etch stop layer is structured. The structuring of the etch stop layer with the pattern of the via structures is carried out as usual by means of a photoresist mask and a selective etching process that does not attack the underlying dielectric. After the stop layer has been etched, the photoresist mask is removed and the upper dielectric layer is deposited, so that a buried, structured etch stop layer is created. This is followed by the production of the photoresist mask with the trench structures. The trenches are aligned with the via openings of the buried stop layer. During the subsequent etching of the dielectric, both the trench and the via structures are produced. After the etching, the photoresist residues are removed and the conductor track metal is deposited (if necessary with a barrier layer system).

The disadvantage of this method is that the via and trench structures need to be very well aligned. Otherwise the vias may be deformed (not round) and the deposition of the diffusion barrier or the filling of the structures is no longer possible in a closed manner. For this reason, this variant is rarely used in production.

Dual damascene process with metallic hard mask

Another process variant is the dual damascene process with a metallic hard mask (English dual damascene patterning with metal hard mask ). A metallic layer deposited on the dielectric serves as a hard mask for the second etching step.

The production sequence begins with the deposition of the dielectric layer, which later contains both the vias and the conductor tracks, initially a metallic layer, often titanium nitride (TiN), applied over the entire surface. This layer, which will later serve as a hard mask, is then structured using photolithography and dry etching with the patterns of the conductor track plane (the trenches ). Now the photoresist layer is removed again.

After the production of the hard mask with the conductor track structures, the production of the via structures continues. For this purpose, the existing layer stack of dielectric and hard mask is coated with a photoresist or photoresist system and this is structured with the via structures. This is followed by the etching of the dielectric and thus the etching of the vias. The hard mask is passive in this step, that is, it does not mask any areas to be etched, since the conductor track structures are larger than the via structures. After the etching, the photoresist layer (vias) is removed again.

In the third sub-step, the conductor track structures are etched using the hard mask. It is recommended that the vias that have already been opened be completely or partially filled with a sacrificial material. Since no etch stop layer is used, the etching of the conductor track structures takes place in a time-controlled manner under known and easily reproducible conditions. After the etching, the photoresist residues are removed and the conductor path metal is deposited (with a barrier layer system).

The advantage of this method is the better integration and less damage to the dielectric through typical methods of photoresist removal, for example oxygen plasma or the UV radiation emitted there, especially when using porous but also dense low-k dielectrics. The main challenges for this process sequence are on the one hand the choice of the hard mask material (etching selectivity, optical transparency for good overlay control but absorbing in the UV range) and on the other hand the hard mask material must be compatible with the copper CMP process.

Use of low-k dielectric as ILD and IMD material

For some years now, so-called low-k dielectrics, i.e. materials with a lower permittivity than silicon dioxide (ε = 3.9), have been used as ILD / IMD materials instead of CVD silicon dioxide in order to reduce parasitic capacitances and thus faster switching times to reach. With these materials, too, a dielectric etch stop layer was (initially) inserted in the middle of the layer stack. However, this has negative consequences with regard to the reduction in the electrical capacitance of the ILD layer system. For example, silicon nitride has a permittivity of approx. 7 and thus lowers the effective permittivity of the layer stack. For a first-generation low-k dielectric such as fluorinated silicate glass (FSG, ε = 3.9), the parasitic capacitances in the layer stack did not decrease in reality compared to a pure silicon dioxide layer (see series connection of capacitors ). This fact also reduces the usefulness of later generation low-k dielectrics, which is why the silicon nitride was replaced by another etch stop material with a lower permittivity in a first step. Above all, silicon carbide (ε = 4.5) and its derivatives have also proven to be very favorable due to other good properties (cf.).

However, as the structures beyond the 130 nm node continued to shrink, the permittivity of silicon carbide was also too high, so process variants without an embedded etch stop layer were developed. Since there is no end point indicator, these variants usually use time-controlled etching processes with a known etching rate in order to produce structures of a defined depth. The floors of the trenches are therefore in the middle of the dielectric. This requires very good control of the etching system as well as high homogeneity on the wafer and from wafer to wafer. Otherwise there could be great differences in the electrical properties of the circuits produced. In addition, other negative effects such as edge rounding or the formation of micro-trenches at the edge corners can occur.

Advantages and disadvantages, areas of application

The dual damascene process is technologically less complex than the simple damascene process. In the dual damascene process, the via and the conductor track level are produced together. A deposition step for the dielectric, the barrier and the conductor track metal can thus be saved. Furthermore, a technically demanding CMP step is not required.

Nevertheless, the dual damascene process is technically more demanding than a double damascene process due to the high demands placed on lithography and the etching processes. However, since the technical challenges can be solved with the same production systems, the lower number of process steps results in lower material and time consumption (higher throughput per system). At the same time, the number of sources of variation is reduced.

The dual damascene technology is usually used for almost all metallization levels of today's integrated circuits (ICs) with copper conductor tracks. Copper is very difficult to dry-etch, diffuses very well in common dielectric materials such as SiO ₂ and must therefore be surrounded on all sides with a diffusion barrier.

literature

Stanley Wolf: Silicon Processing for the VLSI Era. Volume 4 Deep-Submicron Process Technology . Lattice Press, 2002, ISBN 0-9616721-7-X , Chapter 15: Dual-Damascene Interconnects, pp. 671-710 .
Chih-Hang Tung, George T. Sheng, Chih-Yuan Lu: ULSI Semiconductor Technology Atlas . John Wiley & Sons, 2003, ISBN 0-471-45772-8 , pp. 50–52 (short but very clear presentation in technology sections).

Individual evidence

↑ An inter-level dielectric (ILD) refers to the dielectric material between two conductor track levels, i.e. the material in the connecting via layer.
↑ An inter-metal dielectric (IMD) describes the dielectric material between two conductor tracks in the same plane.
^ ^A ^b ^c Stanley Wolf: Silicon Processing for the VLSI Era. Volume 4 Deep-Submicron Process Technology . Lattice Press, 2002, ISBN 0-9616721-7-X , pp. 674-678 .
^ ^A ^b Yoshio Nishi, Robert Doering: Handbook of Semiconductor Manufacturing Technology, Second Edition . CRC Press, 2007, ISBN 978-1-4200-1766-3 , pp. 2-9 .
↑ Patent US6696222 : Dual damascene process using metal hard mask. Published on February 24, 2004 , inventor: Chen-Chiu Hsue, Shyh-Dar Lee. ‌
↑ Krishna Seshan: Handbook of Thin Film Deposition . William Andrew, 2012, ISBN 978-1-4377-7873-1 , pp. 231 .
^ Stanley Wolf: Silicon Processing for the VLSI Era. Volume 4 Deep-Submicron Process Technology . Lattice Press, 2002, ISBN 0-9616721-7-X , pp. 682-683 .

[1] An inter-level dielectric (ILD) refers to the dielectric material between two conductor track levels, i.e. the material in the connecting via layer.

[2] An inter-metal dielectric (IMD) describes the dielectric material between two conductor tracks in the same plane.

[VLSI_Era_V4-3] A ^b ^c Stanley Wolf: Silicon Processing for the VLSI Era. Volume 4 Deep-Submicron Process Technology . Lattice Press, 2002, ISBN 0-9616721-7-X , pp. 674-678 .

[HoSMT-4] A ^b Yoshio Nishi, Robert Doering: Handbook of Semiconductor Manufacturing Technology, Second Edition . CRC Press, 2007, ISBN 978-1-4200-1766-3 , pp. 2-9 .

[5] Patent US6696222 : Dual damascene process using metal hard mask. Published on February 24, 2004 , inventor: Chen-Chiu Hsue, Shyh-Dar Lee. ‌

[6] Krishna Seshan: Handbook of Thin Film Deposition . William Andrew, 2012, ISBN 978-1-4377-7873-1 , pp. 231 .

[VLSI_Era_V4_682-7] Stanley Wolf: Silicon Processing for the VLSI Era. Volume 4 Deep-Submicron Process Technology . Lattice Press, 2002, ISBN 0-9616721-7-X , pp. 682-683 .