Asynchronous processor architecture
Asynchronous processor architecture describes a yet little common processor architecture , which without a central clock gets along. Instead of supplying all components with a common clock signal, the processor is made up of asynchronous circuits that clock themselves. Due to these properties, in contrast to the synchronous processor architecture , a lower power consumption and greater robustness can be achieved in particular.
functionality
Individual asynchronous circuits as logic blocks together form an asynchronous processor. Each of these circuits consists of a logic unit as a data path and a control logic. The data path is responsible for the actual calculations, while the control logic controls the transfer of data between the individual components. This can take place when the logic unit has finished computing and the correct data are in the output register . In addition, the next logic block must be ready to accept new data in the input register.
Delay models
As long as the calculations of a logic unit are still running, the data at the output register are not consistent and can therefore be invalid. There are several delay models to allow the data transfer from the output register to take place at the right moment (list incomplete):
Bounded delay model
When delay bounded model ( engl. "Limited delay") is an upper limit for each data path delay set. This delay represents the maximum time it will take the affected logic unit to complete its calculations. The group is always the worst case ( Engl. "Worst case") is assumed. This means that the worst permissible values for factors that influence the calculation time are used. Such factors can be, for example, temperature, voltage supply or the structure of the data to be calculated.
For each data path, a control logic controls the data transfer to the next logic block by means of the maximum delay time specific for this data path. This is done via a delay element that triggers the handover after the specific delay has expired. Then the following component can continue to work with the data.
This model simplifies the design of asynchronous processors, since existing designs of logic units from synchronous processors can be adopted and embedded in the bounded delay model. This also shows that here the asynchronous behavior does not affect the calculations per se, but only the transfer of data from logic block to logic block.
The data transmission between each bounded delay elements usually regulate micro pipelines ( engl. "Micro-pipes") according to the principle of Ivan Sutherland . These form the asynchronous interface between the components by using a data path based on the bounded delay model. The transmission is then triggered by means of a delay element. The logic for the transmission itself then manages without estimates of delay times.
Delay insensitive circuits
In delay insensitive circuits ( Engl. "Delay-insensitive circuits") is, unlike the bounded delay model, not assumed that the output data after a fixed period of time, be available. Since a reliable data transfer is nevertheless necessary, the stable presence of the valid data at the input of the receiver is recognized. This is implemented with the help of a special coding (e.g. dual rail) of the data and a handshaking protocol (e.g. 2-phase dual rail or 4-phase dual rail). As soon as the recipient has accepted all the data, the sender will receive an acknowledgment of receipt. The implementation of the handshaking protocol and the necessary dual-rail encoding require enormous amounts of additional transistors (factor 2–10). However, delay-insensitive circuits offer advantages: They are extremely robust against external influences, such as temperature changes, changes in the supply voltage or production variations, which can neither be achieved by other asynchronous circuits nor by synchronous circuits.
Quasi delay insensitive circuits
No general circuits can be developed within the delay-insensitive delay model. Only Müller-C elements and inverters are permitted. It is still not allowed that the lines share. In order to develop general circuits, the additional requirement was made that line pitches must be isochronous; H. the signals must arrive at all ends of the line simultaneously.
Dual-rail coding
| X (0) | X (1) | meaning |
|---|---|---|
| 0 | 0 | Empty word |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | error |
With the help of dual-rail coding and a corresponding handshaking protocol, it is possible to identify the completeness of data. This means that each bit is represented by two lines. This creates 4 possible combinations, of which only 2 are required for the actual data. The other two combinations are used for a null word and an error condition.
4-phase dual-rail handshaking protocol
This handshaking protocol is used in delay-insensitive or quasi-delay-insensitive circuits. Together with the dual rail encoding, it can ensure that only fully calculated and therefore valid data is transmitted. As the name suggests, 4 phases are required for the transmission:
- The initial state is that all line pairs are set to 0.
- In the first phase, the data to be sent is applied to the output of the transmitter.
- In the second phase, the recipient accepts the data if he is "free".
- In the third phase, the receiver signals to the sender with an acknowledgment of receipt that it has accepted the data.
- In the fourth phase the transmitter sets its output back to 0. A new cycle can begin.
Current sensing completion detection
When current sensing completion detection ( engl. "Determination of Completion about power consumption measurement") (short: CSCD) method is established the logic unit concerned by measuring the current consumption of the end of the calculations. This is made possible by the fact that the current consumption increases when the gates are switched and falls back to the quiescent level after the switching process.
The problem here, however, is that a reliable measurement is not always possible. If a few bits change, this can lead to a small number of switching operations, which means that the current consumption shows only minor changes. For this case still has a minimum delay generator ( Engl. "Minimum delay generator") are installed, the analogy to the bounded delay triggers the transmission model. This is activated at the beginning of the calculations and triggers the transmission after the longest expected switching time.
This gives a structure that can determine its timing itself, provided that the measurement of the current consumption is successful. The disadvantage of this technology, however, is the increased number of components, since analog components also have to be installed for current measurement.
Practical enforcement
Asynchronous processors are a research area and a lack of experience and development tools are the main obstacles to their increased commercial diffusion. In addition, integration into an environment with synchronous technology has to be achieved for many practical problems.
Asynchronous processors
Some representatives are mentioned here as examples:
| year | processor | Manufacturer | description |
|---|---|---|---|
| 1969 | MU5 | University of Manchester / ICL | an asynchronous mainframe at the University of Manchester |
| 1990 | AMULET 1 | University of Manchester / ARM | an asynchronous ARM processor at the University of Manchester |
| 1997 | nn | Intel | Prototypes of a pentium-compatible chip with an asynchronous design that never leaves the laboratory |
| 1998 | PC5007 | Philips | designed for use in pagers |
| 1998 | PC5010 | Philips | designed for use in pagers |
| 2005 | ACT11 | Epson | first flexible processor for use in e-paper |
| 2006 | ARM996HS | POOR | first commercial non-clocked processor |
literature
- Andreas Bleul et al. a .: How tactless ... The return of asynchronous processors. In: c't magazine. , 17/1999. Heise Zeitschriften Verlag , pp. 176ff., ISSN 0724-8679 .
- Erik Brunvand: Tutorial: Introduction to Asynchronous Circuits and Systems. University of Utah, Salt Lake City 1995.
- Andreas Steininger, Martin Delvai, Wolfgang Huber: Code Alternation Logic (CAL). A Novel Efficient Design Approach for Delay-Insensitive Circuits. Real Time Systems Group TU Vienna , 2004
- Jens Sparsø and Steve Furber (Eds.): Principles of Asynchronous Circuit Design. A Systems Perspective. Kluwer Academic Publ., Boston, Mass. 2001, ISBN 0-7923-7613-7 .
Web links
- The Advanced Processor Technologies Group at the University of Manchester
- Asynchronous Logic at the University of Manchester
- Asynchronous Design Group at Sun Microsystems
- Asynchronous Design Project at Sun Microsystems
- Asynchronous processors SE Seminar in Computer Science, Martin Hudle, Feb. 2, 2000
Individual evidence
- ↑ Article by the Computer Science Institute at the University of Manchester ( Memento of the original from December 9, 2014 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.
- ↑ Data sheet for the PC5007 ( Memento of the original dated August 7, 2004 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. (English)
- ↑ Data sheet for the PC5010 ( Memento of the original dated August 7, 2004 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. (English)
- ↑ ACT11 News Release
- ↑ E-paper boost thanks to flexible microprocessor
