Sun SuperSPARC
The SuperSPARC is a superscalar microprocessor designed by Sun Microsystems . However, since Sun did not have the appropriate manufacturing facilities, the processors were manufactured in the halls of Texas Instruments .
The first processors with the code name Viking were announced in 1991, but delivery of the first SPARCstation 10 did not begin until May 1992. In the course of 1994, the slightly improved successor SuperSPARC II was presented.
history
After the platform change to the Sun-4 series began in 1987, the development of a multi-processor-compatible successor to the current SPARC V7 generation began shortly thereafter . The aim was to develop a modern superscalar processor which, according to application analyzes by Sun, works most effectively with three commands per cycle, has an integrated cache and the most effective pipeline possible . In addition to the points already mentioned, this processor concept also offered an integrated floating point unit and the connection of an optional cache controller compared to its predecessor . This in turn should be able to address a large L2 cache. Production was supposed to start in 1990, but was repeatedly postponed due to manufacturing difficulties.
While the MicroSPARC served the segment for uniprocessor systems at Sun, the SuperSPARC was used as a multiprocessor for workstations and supercomputers according to its development . Most of the processors built were used in the SparcStation 10/20 and in the replicas made by other manufacturers. It is also worth mentioning that it is used in the most powerful servers Sun SparcCenter 2000, Cray CS6400 and Thinking Machines CM-5E , each with up to 20, 64 or 128 processors.
As the successor to the SuperSPARC, the UltraSPARC was supposed to start in 1994 , but the delivery of the first machines was delayed until winter 1995. The SuperSPARC could not fill the gap that had arisen, as it tended to overheat in some machines at 85 MHz and therefore only operated in certain servers. In order to be able to continue to compete with other systems, the HyperSPARC was offered, which until then had been positioned as a SuperSPARC competitor on this platform.
architecture
The microprocessor is based on the specifications of the SPARC V8 processor architecture and therefore inherits all properties. The basic structure is a triple, superscalar 32-bit processor core with two integer units (IU) and a floating point unit (FPU). The integer units have a 4-stage pipeline and enable the SuperSPARC to perform up to two integer operations per cycle. This high throughput is rarely achieved in real situations due to program branching and data dependencies. However, in order to increase the maximum yield, the techniques branch prediction and data forwarding were implemented in the processor.
The floating point unit consists of two independent pipelines, a floating point adder (FADDER) for addition, subtraction and logical operations, a floating point multiplier (MULTIPLIER) for multiplications and a floating point controller . Each of the two processing units is assigned to one of the pipelines and is filled with data as required. The floating point controller takes all floating point instructions from the last pipeline stage of the IU, decides on the basis of the type of instruction which execution unit is responsible for the instruction and fills the corresponding pipeline.
Like every SPARC, the SuperSPARC has a large register field of 128 integer and 32 floating point registers, which cannot be addressed directly, but only via the corresponding register window. There are also eight global registers.
The SuperSPARC II improved some aspects of the design. The floating point unit received a further unit, the floating point divide / square root (FDS) for division and square root calculations and thus also a third pipeline. In addition, the integer register field has been revised to make it easier to increase the clock rate.
Models
SuperSPARC (Viking)
- L1 cache: 20 KB (data) + 16 KB (instructions)
- L2 cache: none, 1MB, or 2MB
- SPARC V8
- MBus / XBus
- Release DATE: 1991
- Manufacturing technology: 0.8 µm BiCMOS
- Number of transistors: 3.1 million
- Clock rates: 33–60 MHz
- Model numbers
- SM20: 1 CPU, no L2 cache, 33 MHz bus: 33 MHz
- SM21: 1 CPU, 1 MB L2 cache, 33 MHz bus: 33 MHz
- SM30: 1 CPU, no L2 cache, 36 MHz bus: 36 MHz
- SM40: 1 CPU, no L2 cache, 40 MHz bus: 40 MHz
- SM41: 1 CPU, 1 MB L2 cache, 40 MHz bus: 40 MHz
- SM50: 1 CPU, no L2 cache, 50 MHz bus: 50 MHz
- SM51: 1 CPU, 1 MB L2 cache, 50 MHz bus: 40 MHz
- SM51-2: 1 CPU, 2 MB L2 cache, 50 MHz bus: 40 MHz
- SM52: 2 CPU, 1 MB L2 cache, 45 MHz bus: 40 MHz
- SM52X: 2 CPUs, 1 MB L2 cache, 50 MHz bus: 40 MHz
- SM61: 1 CPU, 1 MB L2 cache, 60 MHz bus: 50 MHz
- SM61-2: 1 CPU, 2 MB L2 cache, 60 MHz bus: 50 MHz
SuperSPARC II (Voyager)
- L1 cache: 20 KB (data) + 16 KB (instructions)
- L2 cache: 1 MB or 2 MB
- SPARC V8
- MBus / XBus
- Release DATE: 1994
- Manufacturing technology: 0.8 µm BiCMOS
- Number of transistors: 3.1 million
- Clock rates: 75–90 MHz
- Model numbers
- SM71: 1 CPU, 1 MB L2 cache, 75 MHz bus: 50 MHz
- SM81: 1 CPU, 1 MB L2 cache, 85 MHz bus: 50 MHz
- SM81-2: 1 CPU, 2 MB L2 cache, 85 MHz bus: 50 MHz
- SM91-2: 1 CPU, 2 MB L2 cache, 90 MHz bus: 50 MHz
swell
literature
- SPARC International Inc .: The SPARC Architecture Manual Version 8, 1991
- Sun Microsystems Computer Corporation: The SuperSPARC Microprocessor - Technical White Paper, 1992
- Sun Microsystems Computer Corporation: The SuperSPARC II Microprocessor - Technical White Paper, 1995