Larrabee (microarchitecture) and 1940 in chess: Difference between pages

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{{year nav topic|1940|chess}}
{{future chip}}
Events in [[chess]] in [[1940]]
[[Image:Larrabee slide block diagram.jpg|320px|thumb|The '''Larrabee GPU''' architecture, unveiled at the [[SIGGRAPH]] conference in August 2008.]]


==Chess events in brief==
'''Larrabee''' is the [[Codename|codename]] for a [[graphics processing unit|graphics processing unit (GPU)]] chip that [[Intel]] is developing separately from its [[Intel GMA|current line of integrated graphics accelerators]]. The [[video card]] containing Larrabee is expected to compete with [[GeForce]] and [[Radeon]] products from [[NVIDIA]] and [[Advanced Micro Devices|AMD/ATI]] respectively. Larrabee will also compete in the [[GPGPU]] and [[high-performance computing]] markets. Intel plans to have engineering samples of Larrabee ready by the end of 2008, with a [[video card]] hitting shelves in late 2009 or 2010.<ref>{{cite web|url=http://beyond3d.com/content/news/565|title=Larrabee: Samples in Late 08, Products in 2H09/1H10|accessdate=2008-01-17|publisher=''beyond3d.com''}}</ref>
* 17 January 1940 - [[Dawid Przepiórka]], [[Stanisław Kohn]], [[Moishe Lowtzky]], [[Achilles Frydman]], Abkin, Młynek, Zahorski and many others were arrested at the Kwieciński Chess Café in Warsaw, and imprisoned at Daniłowiczowska Str. (they had played a prison tournament won by Lowtzky there). Later (February – March 1940) most of them (all Jewish) were killed in a mass execution by the Nazis in [[Palmiry]], [[General Government]].<ref>Tadeusz Wolsza, ''Arcymistrzowie, mistrzowie, amatorzy... Słownik biograficzny szachistów polskich'', Wydawnictwo DiG, Warszawa 1995 (tom 1), 1996 (t.2), 1999 (t.3)</ref>
* September 1940 - National Chess Centre burnt down in London after an air raid ([[World War II]]).<ref>http://www.geocities.com/SiliconValley/Lab/7378/history.txt</ref>


==Tournaments==
==Comparison with competing products==
* [[Beverwijk]] (the 3rd ''Hoogovenschaaktoernoi'') won by [[Max Euwe]], January 1940.
* [[Budapest]] (''Maroczy Jubilaeum'') won by Euwe followed by [[Milan Vidmar]], [[Gedeon Barcza]], etc.
* [[Buenos Aires]] (the 19th ''Argentina Mayor'') won by [[Aristide Gromer]] followed by [[Franciszek Sulik]], [[Carlos Guimard]], etc.
* [[Havana]] won by [[Isaac Kashdan]] ahead of [[Georges Koltanowski]]
* [[London]] (''Easter'') won by [[Harry Golombek]] and [[Paul List]] ahead of [[Vera Menchik|Vera Menchik-Stevenson]]
* [[Bad Elster]] won by [[Karl Gilg]] and [[Ludwig Roedl]], start 14 May 1940.
* [[Berlin]] won by [[Efim Bogoljubow]] ahead of [[Kurt Richter]], start 16 June 1940.
* [[New York]] (the 3rd [[U.S. Chess Championship]]), won by [[Samuel Reshevsky]]
* [[Dallas]] (the 41st [[U.S. Open Chess Championship|U.S. Open]]), won by [[Reuben Fine]], August 1940.
* [[Bad Oeynhausen]] (the 7th [[German Chess Championship]]), won by [[Georg Kieninger]] ahead of [[Paul Felix Schmidt]], start 4 August 1940.
* [[Rakovnik]] (the [[Czech Chess Championship|Bohemia and Moravia Chess Championship]]), won by [[Jan Foltys]]
* [[Leningrad]] (the 15th [[Leningrad City Chess Championship]]) won by [[Ilya Rabinovich]]
* [[Moscow]] (the 12th [[USSR Chess Championship]]), won jointly by [[Igor Bondarevsky]] and [[Andor Lilienthal]], 5 September – 3 October 1940.
* [[Kiev]] (the 12th [[Ukrainian Chess Championship]]), won by [[Isaac Boleslavsky]] ahead of [[David Bronstein]]
* [[Krakow]]/[[Krynica]]/[[Warsaw]] (the 1st [[General Government chess tournament|General Government Chess Championship]]), won by Bogoljubow and [[Anton Kohler]], 3–17 November 1940.


==Matches==
[[Image:Slide convergence.jpg|300px|thumb|Larrabee has a fully programmable pipeline, in contrast to current generation graphics cards which are only partially programmable.]]
* [[Paul Keres]] won against [[Max Euwe]] (7.5 : 6.5) in The Netherlands (various places) in 1939/40.<ref>http://xoomer.alice.it/cserica/scacchi/storiascacchi/matches/1930-49.htm</ref>
* [[Carlos Maderna]] defeated [[Luis Piazzini]] (8 : 6), Buenos Aires, Argentina (the 18th ARG-ch).
* [[Walter Cruz]] beat [[Octavio Trompowsky]] (5.5 : 1.5), Rio de Janeiro, Brazil.
* [[Georg Kieninger]] defeated [[Wilhelm Ernst (chess player)|Wilhelm Ernst]] (6 : 4), Cologne, Germany.
* [[Mikhail Botvinnik]] beat [[Viacheslav Ragozin]] (7 : 3), Leningrad, Russia.


==Deaths==
Larrabee can be considered a hybrid between a [[multi-core]] [[CPU]] and a [[GPU]], and has similarities to both. Its [[cache coherency|coherent cache]] hierarchy and [[x86 architecture]] compatibility are CPU-like, while its wide [[SIMD]] vector units and texture sampling hardware are GPU-like.
* ca. March 1940 - [[Dawid Przepiórka]] killed in a mass execution by the Nazis in [[Palmiry]].

* ca. March 1940 - [[Achilles Frydman]] killed in a mass execution in Palmiry.
As a GPU, Larrabee will support traditional rasterized [[3D graphics]] ([[DirectX]]/[[OpenGL]]) for games. However, Larrabee's hybrid of CPU and GPU features should be suitable for [[GPGPU|general purpose GPU]] (GPGPU) or [[stream processing]] tasks.<ref>{{citeweb|title=First Details on a Future Intel Design Codenamed 'Larrabee'|url=http://www.intel.com/pressroom/archive/releases/20080804fact.htm|publisher=''[[Intel]]''|accessdate=2008-09-01}}</ref> For example, Larrabee might perform [[Ray tracing (graphics)|ray tracing]] or [[physics processing]],<ref>{{cite web|url=http://arstechnica.com/news.ars/post/20070917-intel-picks-up-gaming-physics-engine-for-forthcoming-gpu-product.html|title=Intel picks up gaming physics engine for forthcoming GPU product|accessdate=2007-09-17|publisher=''[[Ars Technica]]''|first=Jon|last=Stokes}}</ref> in [[real time]] for games or offline for scientific research as a component of a [[supercomputer]].<ref>{{cite web |last=Stokes|first=Jon|title=Clearing up the confusion over Intel's Larrabee|publisher=''[[Ars Technica]]''|url=http://arstechnica.com/articles/paedia/hardware/clearing-up-the-confusion-over-intels-larrabee.ars|accessdate=2007-06-01}}</ref> In the [[high-performance computing]] market Intel's CPUs are in some cases being displaced by GPGPU products like [[NVIDIA Tesla]] and [[AMD FireStream]] (for example in the #2 supercomputer on the [[TOP500]] list<ref>http://news.softpedia.com/news/Nvidia-Tesla-GPGPU-Shows-Up-in-Bull-039-s-NovaScale-Supercomputer-84089.shtml</ref>); Larrabee is Intel's answer to GPGPU.<ref name="inquirer">{{cite web|url=http://www.theinquirer.net/en/inquirer/news/2007/04/03/gpgpu-vs-cpu-will-be-the-war-of-2008-9 |title=GPGPU vs. CPU will be the war of 2008-9 |publisher=The Inquirer |author=Theo Valich |date = 03 April 2007 |accessdate=2008-08-24}}</ref>
* ca. March 1940 - [[Stanisław Kohn]] killed in a mass execution in Palmiry.

* ca. March 1940 - [[Moishe Lowtzky]] killed in a mass execution in Palmiry.
===Differences with current GPUs===
* 11 September 1940 - [[Peter Fyfe]] died in Glasgow, Scotland. Fyfe gambit.

Larrabee will differ from other discrete GPUs currently on the market such as the [[GeForce 200 Series]] and the [[Radeon R700|Radeon 4000 series]] in three major ways:

* Larrabee will use the [[x86]] instruction set with Larrabee-specific extensions.<ref name="siggraph"/>

* Larrabee will feature [[cache coherency]] across all its cores.<ref name="siggraph"/>

* Larrabee will include very little specialized graphics hardware, instead performing tasks like z-buffering, clipping, and blending in software, using a tile-based rendering approach.<ref name="siggraph"/> A renderer implemented in software can more easily be modified, allowing more differentiation in appearance between games or other 3D applications. Intel's [[SIGGRAPH|SIGGRAPH 2008]] paper<ref name="siggraph"/> mentions order-independent transparency, [[irregular Z-buffer]]ing, and real-time [[raytracing]] as rendering features that can be implemented with Larrabee.

===Differences with CPUs===
The x86 processor cores in Larrabee will be different in several ways from the cores in current Intel CPUs such as the [[Intel Core 2|Core 2 Duo]]:

* Larrabee's x86 cores will be based on the much simpler [[Pentium]] P54C design which is still being maintained for use in [[embedded system|embedded]] applications. <ref name="sorta">{{citeweb|title=Intel's Larrabee GPU based on secret Pentagon tech, sorta [Updated]|url=http://arstechnica.com/news.ars/post/20080708-intels-larrabee-gpu-based-on-secret-pentagon-tech-sorta.html|publisher=''[[Ars Technica]]''|accessdate=2008-08-06}}</ref> The P54C-derived core is [[superscalar]] but does not include [[out-of-order execution]], though it has been updated with modern features such as [[x86-64]] support, <ref name="siggraph"/> similarily to [[Intel Atom]]. In-order execution means lower performance for individual cores, but since they are smaller, more can fit on a single chip, increasing overall throughput.

* Each Larrabee core contains a 512-bit vector processing unit, able to process 16 single precision floating point numbers at a time. This is similar to but four times larger than the [[Streaming SIMD Extensions|SSE]] units on most x86 processors, with additional features like [[scatter/gather]] instructions and a mask register designed to make using the vector unit easier and more efficient. Larrabee derives most of its number-crunching power from these vector units.<ref name="siggraph">{{citeweb|title=Larrabee: A Many-Core x86 Architecture for Visual Computing|url=http://softwarecommunity.intel.com/UserFiles/en-us/File/larrabee_manycore.pdf|publisher=''[[Intel]]''|accessdate=2008-08-06|doi=10.1145/1399504.1360617}}</ref>

* Larrabee includes one major fixed-function graphics hardware feature: texture sampling units. These perform [[trilinear filtering|trilinear]] and [[anisotropic filtering]] and [[texture compression|texture decompression]].<ref name="siggraph"/>

* Larrabee has a 1024-bit (512-bit each way) ring bus for communication between cores and to memory.<ref name="siggraph"/> This bus can be configured in two modes to support Larrabee products with 16 cores or more, or fewer than 16 cores.<ref name="glaskowsky">{{cite web |last=Glaskowsky|first=Peter|title=Intel's Larrabee--more and less than meets the eye|url=http://news.cnet.com/8301-13512_3-10006184-23.html|publisher=''[[CNET]]''|accessdate=2008-08-20}}</ref>

* Larrabee includes explicit cache control instructions to reduce [[cache thrashing]] during streaming operations which only read/write data once.<ref name="siggraph"/>

* Each core supports 4-way simultaneous multithreading, with 4 copies of each [[processor register]].<ref name="siggraph"/>

Theoretically Larrabee's x86 processor cores can run existing PC software; even operating systems. However, Larrabee's video card will not include all the features of a PC-compatible motherboard, so PC operating systems and applications will not run without modifications. A different version of Larrabee might sit in motherboard CPU sockets using [[Intel QuickPath Interconnect|QuickPath]]<ref>{{cite web |last=Stokes|first=Jon|title=Clearing up the confusion over Intel's Larrabee, part II|url=http://arstechnica.com/news.ars/post/20070604-clearing-up-the-confusion-over-intels-larrabee-part-ii.html|publisher=''[[Ars Technica]]''|accessdate=2008-01-16}}</ref>, but Intel has not yet announced plans for this. Even if compatibility is achieved, to run efficiently software must be rewritten to use Larrabee's vector units, and not all software can put them to good use.<ref name="siggraph"/>

===Comparison with the Cell Broadband Engine===

Larrabee's philosophy of using many small, simple cores has similarities to the ideas behind the [[Cell (microprocessor)|Cell processor]]. However, there are differences in implementation.

* The Cell processor includes one main processor which controls many smaller processors. In contrast, all of Larrabee's cores are the same, which can be useful for various purposes such as load balancing and task migration.<ref name="siggraph"/>

* Cell and Larrabee both use a high-bandwidth ring bus to communicate between cores.<ref name="siggraph"/>

* Each compute core in the Cell (SPE) has a local store, for which explicit operations ([[Direct Memory Access|DMA]]) are used for flexible data transfer without allowing direct access (load/store) from other cores. In Larrabee, all on-chip and off-chip memories are under automatically-managed [[memory hierarchy|coherent cache hierarchy]], so that its cores virtually share a uniform memory space through standard load/store instructions.<ref name="siggraph"/>.

* Because of cache coherence noted above, each program running in Larrabee has virtually a large linear memory just as in traditional general-purpose CPU; whereas an application for Cell should be programmed taking into consideration limited memory footprint of the local store associated with each SPE (for details see [[Cell (microprocessor)#Overview|this article]]) but with theoretically higher bandwidth.

* Cell uses [[Direct Memory Access|DMA]] for data transfer to/from on-chip local memories, which has a merit in flexibility and throughput; whereas Larrabee uses special instructions for cache manipulation (notably cache eviction hints and pre-fetch instructions), which has a merit in that it can maintain [[cache coherency|cache coherence]] (hence the standard [[memory hierarchy]]) while boosting performance for e.g. rendering pipelines and other stream-like computation.<ref name="siggraph"/>.

===Comparison with Intel GMA===
Intel currently sells a line of GPUs under the [[Intel GMA]] brand. These chips are not sold separately but are integrated onto motherboards. Though the low cost and [[CPU power dissipation|power consumption]] of Intel GMA chips make them suitable for small laptops and less demanding tasks, they lack the 3D graphics processing power to compete with NVIDIA and AMD/ATI for a share of the high-end gaming computer market, the [[high-performance computing|HPC]] market, or a place in popular [[video game console]]s. In contrast, Larrabee will be sold as a discrete GPU, separately from motherboards, and is expected to have performance good enough for consideration in the next generation of video game consoles.<ref>{{cite web|url=http://www.totalvideogames.com/news/Intels_Larrabee_Shaping_Up_For_Next-Gen_Consoles_13643_6321_0.htm |title=Intel's Larrabee Shaping Up For Next-Gen Consoles? |author=Chris Leyton |date=2008-08-13 |accessdate=2008-08-24}}</ref>

The team working on Larrabee is separate from the [[Intel GMA]] team. The hardware is being designed by Intel's [[Hillsboro, Oregon]] design team, whose last major design was the [[Pentium 4]]. The software and drivers are being written by a newly-formed team. The 3D stack specifically is being written by developers at [[RAD Game Tools]] (including [[Michael Abrash]]).<ref>[http://anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3367 AnandTech: Intel's Larrabee Architecture Disclosure: A Calculated First Move]</ref>

==Preliminary performance data==

[[Image:Slide scaling.jpg|300px|thumb|[[Benchmarking]] results from the recent SIGGRAPH paper, showing performance as an approximate linear function of the number of processing cores.]]

Intel's [[SIGGRAPH]] 2008 paper describes simulations of Larrabee's projected performance.<ref name="siggraph"/> Graphs show how many 1 GHz Larrabee cores are required to maintain 60 FPS at 1600x1200 resolution in several popular games. Roughly 25 cores are required for [[Gears of War]] with no antialiasing, 25 cores for [[F.E.A.R]] with 4x antialiasing, and 10 cores for [[Half-Life 2: Episode 2]] with 4x antialiasing. It is likely that Larrabee will run faster than 1 GHz, so these numbers are conservative.<ref>{{cite web|url=http://www.tomshardware.com/news/intel-larrabee-idf,6210.html |title=Intel's 'Larrabee' to Shakeup AMD, Nvidia |publisher=Tom's Hardware |date=August 20, 2008 |author=Steve Seguin |accessdate=2008-08-24}}</ref> Another graph shows that performance on these games scales perfectly linearly with the number of cores up to 32 cores. At 48 cores the performance scaling is roughly 90% of linear.

A June 2007 PC Watch article suggests that the first Larrabee chips will feature 32 x86 processor cores and come out in late 2009, fabricated on a [[45 nanometer|45 nanometer process]]. Chips with a few defective cores due to [[Semiconductor device fabrication|yield]] issues will be sold as a 24-core version. Later in 2010 Larrabee will be shrunk for a [[32 nanometer|32 nanometer fabrication process]] which will enable a 48 core version.<ref>{{citeweb|title= Intel is promoting the 32 core CPU "Larrabee"|url=http://pc.watch.impress.co.jp/docs/2007/0611/kaigai364.htm|publisher=''pc.watch.impress.co.jp''|accessdate=2008-08-06}}{{ja}}[http://translate.google.com/translate?u=http%3A%2F%2Fpc.watch.impress.co.jp%2Fdocs%2F2007%2F0611%2Fkaigai364.htm&sl=ja&tl=en|English <small>translation</small>]</ref>

Fudzilla has posted several short articles about Larrabee, claiming that Larrabee may have a [[thermal design power|TDP]] as large as 300[[Watts|W]],<ref>{{citeweb|title=Larrabee to launch at 300W TDP|url=http://www.fudzilla.com/index.php?option=com_content&task=view&id=7651&Itemid=1|publisher=''fudzilla.com''|accessdate=2008-08-06}}</ref> that Larrabee will use a 12-layer [[printed circuit board|PCB]] and has a cooling system that "is meant to look similar to what you can find on high-end Nvidia cards today,"<ref>{{citeweb|title=Larrabee will use a 12-layer PCB|url=http://www.fudzilla.com/index.php?option=com_content&task=view&id=8435&Itemid=1|publisher=''fudzilla.com''|accessdate=2008-08-06}}</ref> that Larrabee will use [[GDDR5]] memory, and that it is targeted to have 2 [[single-precision]] [[FLOPS|teraflops]] of computing power.<ref>{{citeweb|title=Larrabee will use GDDR5 memory|url=http://www.fudzilla.com/index.php?option=com_content&task=view&id=8460&Itemid=1|publisher=''fudzilla.com''|accessdate=2008-08-06}}</ref>

==Criticism==
Larrabee's early presentation has drawn some criticism from competitors. At [[Nvision|NVISION 08]], several [[NVIDIA]] employees called the [[Siggraph]] paper "marketing puff" and told the press that the Larrabee architecture was "like a [[GPU]] from 2006".<ref>[http://www.pcpro.co.uk/news/220947/nvision-larrabee-like-a-gpu-from-2006.html NVISION 08, "Larrabee like a GPU from 2006"]</ref>

== See also ==
* [[Intel740]]
* [[Intel GMA]]
* [[x86 architecture]]
* [[x86-64]]
* [[Pentium|P5]]
* [[List of Intel CPU microarchitectures]]


==References==
==References==
{{reflist}}
{{reflist}}

==External links==
==External links==
[http://www.rogerpaige.me.uk/tables11.htm 1940 crosstables]
*[http://www.intel.com/pressroom/archive/releases/20080804fact.htm Intel fact sheet about Larrabee]
*[http://softwarecommunity.intel.com/UserFiles/en-us/File/larrabee_manycore.pdf Intel's SIGGRAPH 2008 paper on Larrabee]
*[http://techgage.com/article/intel_opens_up_about_larrabee/ Techgage.com - Discusses how Larrabee differs from normal GPUs, includes block diagram illustration]
*[http://anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3367 Intel's Larrabee Architecture Disclosure: A Calculated First Move]

{{Intel processors}}

[[Category:Intel x86 microprocessors]]
[[Category:Intel microprocessors]]
[[Category:Graphics cards]]


[[Category:1940 in chess|*]]
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Revision as of 19:34, 10 October 2008

List of years in chess (table)
+...

Events in chess in 1940

Chess events in brief

Tournaments

Matches

Deaths

References

  1. ^ Tadeusz Wolsza, Arcymistrzowie, mistrzowie, amatorzy... Słownik biograficzny szachistów polskich, Wydawnictwo DiG, Warszawa 1995 (tom 1), 1996 (t.2), 1999 (t.3)
  2. ^ http://www.geocities.com/SiliconValley/Lab/7378/history.txt
  3. ^ http://xoomer.alice.it/cserica/scacchi/storiascacchi/matches/1930-49.htm

External links

1940 crosstables

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