Boundary Scan Test

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Boundary scan and boundary path scanning are synonymous terms for a standardized method for testing digital and analog components in electronics .

Due to the complexity and smallness of today's circuit structures, it is becoming more and more difficult to physically access certain points on a circuit. The interconnection of circuit boards is increasingly carried out via additional internal connecting lines. So-called multi-layer boards (Engl. Multilayer PCBs ), up to 20 have such wiring levels. In addition, integrated circuits (ICs) with a large number of pins are often supplied in housings that make mechanical access impossible, since all connections are hidden under the housing. It is therefore necessary to test circuit boards without direct physical access, as is necessary for an in-circuit test, for example . The process known as Boundary Scan was mainly developed in Europe ( Philips ) and is now internationally standardized .

The boundary scan method uses additional cells (latches), with the help of which signals can be injected into the circuit to be tested from outside via predefined paths. The signals from the circuit that are applied to pins of the IC can be detected via the scan path. The latches are passive in normal operation. There is no difference to ICs without boundary scan functionality; the connections of the chip are only connected to the pins of the IC. In test operation, they are actively controlled according to the procedure.

In order to enable the use of the boundary scan method in an integrated circuit, (at least) corresponding special modifications are built into the inputs and outputs of highly integrated components. A boundary scan cell is installed at each input or output of an IC. All boundary scan cells are linked in series to form a chain that encompasses the entire I / O structure of the integrated circuit. The IC has at least four specially reserved control and data pins. These are test data input (TDI) and output (TDO), a test pulse (TCK) and a test mode select connection (TMS) as well as the optional test reset input (TRST). These pins together make up the Test Access Port (TAP). This is a synchronous finite state machine (engl. Finite state machine , FSM) with 16 possible states.

The test data are passed on via TDI / TDO . TMS is used to distribute control commands which individually set the desired test mode for each integrated circuit. With the rising edge of TCK, the external data from TDI is read into the corresponding register . TRST is used to initialize the FSM.

Scan chain from three test devices

The actual scan chain starts with the TDI input pin of the circuit. This is connected to the TDO of the boundary scan test device via the connector on the circuit board. The chain is continued by connecting the TDO outputs of the individual ICs to the TDI of the next IC. At the end of the chain, the last TDO output is connected to the TDI of the boundary scan test device via the connector. TMS, TCK and optionally TRST are connected in parallel from all ICs to the corresponding pins on the connector.

TDI and TDO data are serially pushed in and out of the input scan cells (scan chain, see scan test ) using a shift function . When all TDI data have been clocked in, they are output in parallel to the circuit arrangement to be tested. The response signal can then be recorded by the output scan cells and read out serially. The scan cells are usually located on the I / O pins , which can thus be bypassed. The boundary scan principle avoids contacting a large number of pins and thus possible contact errors and easily reaches (partial) circuits inside a chip. Usually a large number of scan chains are operated in parallel.

With the help of the boundary scan functionality, connections between pins can be checked with the boundary scan function. It is also possible to detect short circuits between these pins. External programmable memories can also be programmed with the aid of the boundary scan output cells. Typically this is a flash memory . Due to the detour via the scan chain, this method is slower than other programming methods and is therefore only suitable for smaller amounts of data. Volatile memories can be checked by programming and then reading out bit patterns via the boundary scan cells. This means that your soldered connections can also be checked. This method is used, for example, with RAM memories.

The JTAG standard IEEE 1149.1 defines the specifications of the TAP bus and the scan cells. This standard is supplemented by the P1500 standard for backplane testing to test many different systems in an electronic unit over the same interface.

The JTAG standard IEEE 1149.4 has now been defined for testing analog signals .

AC-coupled or differential signals can be tested using the JTAG standard IEEE 1149.6.

Functional extensions

Beyond pure test function also continuously provide many memory chips with Boundary Scan TAP on the bus also opportunities to the relevant element in the circuit (Engl. In-circuit ) to program. In the case of microprocessors , diagnostic programs for debugging and troubleshooting can also run via the connection, usually referred to as the JTAG interface . This eliminates the need for special and usually expensive in-circuit emulators . However, all of these expansions are implemented by special, mostly undocumented commands on the TAP bus and are highly manufacturer and module-specific.

integration

Every test procedure has its limits in terms of test coverage and error detection or diagnosis. In addition, there is the increasing complexity of current and, above all, future assemblies. Designs such as BGA , µBGA or flip chip hardly allow any mechanical access. In order to achieve an optimal or maximum test depth, it makes sense to combine test methods with one another. Boundary Scan can be integrated into ATE systems such as in-circuit testers , flying probe testers, functional test systems or AOI systems as an option for greater test and fault coverage .

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