Fine wiring

Fine wiring is a step in the layout design of integrated circuits of a circuit . Here, the individual signal networks, which were previously laid on approximate wiring paths for the global wiring, are assigned a specific geometry on the levels available to the layouts.

Basics

In the fine wiring, a set of signal networks is given, their connections during placement were assigned on the wafer geometry. These need to be connected in an electrically conductive manner on other levels that are deposited on the wafer surface. For this purpose, electrically conductive and electrically insulating layers are deposited alternately using mask-based processes and etched within specific areas using photolithography. The wiring levels are electrically connected to one another by means of VIAs in areas exposed by the etching.

Depending on the technology used, different boundary conditions must be observed when wiring. Different algorithms are used for fine wiring, also depending on the technological resources available.

A preferred direction is usually defined on the electrically conductive levels. This then changes alternately on the electrically conductive levels above. This results in both technological and algorithmic simplifications.

Detailed wiring methods

For the given wiring resources, algorithms can be developed, taking into account the technology rules, that generate possible layouts for the wiring. This wiring can be used to generate masks that can be used within a semiconductor process to produce the circuit.

The algorithms used often subdivide the graph into discrete areas that imply the technology rules, which requires a discrete raster graph as the basis for the wiring algorithms. However, especially with ever smaller technologies, it is necessary to continuously consider the chip area in order to do justice to the advantages of scaling.

Channel and switch box wiring

Historically, integrated circuits have long been fabricated by two levels of wiring deposited over the wafer. This led to special algorithms that made assumptions optimized for a vertical and a horizontal plane.

Specifically, the chip area to be wired was subdivided into channels (two neighbors) or switch boxes (three or four neighbors) depending on the number of neighboring standard cells or macros placed on the wafer level. A number of algorithms adapted to the limited resources are available for this.

Surface wiring

In more modern circuits, due to several wiring levels available for wiring, more general algorithms must be used for wiring than when wiring on two levels.

Specialized route search algorithms are often the basis for fine wiring on several levels (for example A * - or the Dijkstra algorithm ).

literature

J. Lienig: Layout Synthesis of Electronic Circuits - Basic Algorithms for Design Automation. 2nd edition, Springer, Berlin / Heidelberg / New York 2016, ISBN 978-36-624-9814-9 .
Tim Nieberg: Gridless Pin Access in Detailed Routing , (as of June 27, 2017)

Individual evidence

↑ As the feature size become ever smaller, shifts towards gridless design paradigms are necessary and a formerly trivial task, namely pin access, now becomes difficult.

[1] As the feature size become ever smaller, shifts towards gridless design paradigms are necessary and a formerly trivial task, namely pin access, now becomes difficult.