Load-Link / Store-Conditional
Load Link / Store Conditional ( LL / SC ) (. English about the "Load Reference / write conditional") is a pair of processor - commands , a read-modify-write implement operation. The LL command loads a memory location, its content can be changed, and the SC command writes the new value back into the referenced memory location, provided that this has not been changed . If the memory location has been changed, the write operation will fail. There are strong and weak semantics for the degree of change (see below).
LL / SC operations are used to implement atomic operations without the use of locks ( lock-free ). By linking read and write operations, their semantics are more narrowly defined than with the compare-and-swap operation, as this cannot recognize (non-changing) access to the referenced memory location.
Implementations of the LL / SC command pair exist on different computer architectures , including: ldl_l / stl_c and ldq_l / stq_c ( Alpha processor ), lwarx / stwcx ( PowerPC ), ll / sc ( MIPS architecture ), and ldrex / strex ( ARM Architecture from version 6). These architectures are mostly based on the RISC philosophy, the instruction set of which reduces memory access to read and write commands .
Strong and weak semantics
In the narrow interpretation of the semantics, the LL / SC command pair only fails if the referenced memory location is accessed between the LL and SC commands.
On many architectures, however, other events also lead to a superfluous failure, for example in the case of context changes , interrupts or other memory accesses.