Parallax propeller

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Parallax propeller

The Parallax Propeller is an established in 2006 microcontroller with eight independently operating 32-bit - RISC CPU cores. The manufacturer's name is P8X32A. The second chip in the family is currently in development.

The idea behind the product is that instead of specialized IO components (timer, PWM, UART) one of the cores can take on this task, which allows more flexibility, as you do not have to rely on the functions that the manufacturer has built in.

The propeller is programmed in the specially developed high-level language SPIN and in assembler . The high-level language Spin is not translated into machine code , but transformed into an intermediate code ( bytecode ) that is processed by a bytecode interpreter in the processor. Parallax provides the "Propeller Tool" free of charge as an integrated development environment.

Both the processor and the SPIN programming language (including compiler and byte code interpreter) were developed by Chip Gracey , the co-founder and current chairman of Parallax.

The propeller can now also be programmed in other languages ​​such as BASIC , C or Forth ; various compilers exist as free software and as commercial products.

Multi-core architecture

Each of the eight 32-bit cores, also known as Cog , has an elementary ALU that does not directly support division, as well as a RAM for 512 32-bit-wide long words (altogether 2  KiB ) in the executable code as well Data can be stored. Self-modifying code is therefore possible and this option is also used. (For example, by an instruction that is used to create a return mechanism after a call to a subroutine that works without a stack.)

Furthermore, each CPU core has exclusive access to all I / O pins (32 in total), to two independently configurable counters (can be used as counter, timer or numerically controlled oscillator ; also as an analog-to-digital converter according to the sigma-delta Process and vice versa to use as a digital-to-analog converter using pulse width modulation ) and to a video generator (generates RGB signals for direct control of a computer display or composite signals for a television set according to the NTSC or PAL standard).

The shared resource is a memory of 64  KiB , the lower half of which is designed as RAM and the upper half as ROM . In order to ensure that no more than one cog accesses this memory at the same time, the so-called round robin method is used, in which each cog can exclusively access the shared memory for a small time window before it is the turn of the next cog . This multiplexer is also referred to as a hub by Parallax in this context .

Speed ​​and energy management

The system clock can be generated internally or externally. It can be increased by a factor of 1, 2, 4, 8 or 16 using a PLL clock multiplier integrated on the chip .

The PLL multiplier value can be changed at runtime, which can increase energy efficiency. For example, the multiplier can be reduced before a longer waiting time, required for timing reasons, is inserted without the execution of an instruction. The multiplier can then be increased again. The processor therefore consumes less energy. However, use of this technique is limited to situations where no other cog is running timing-sensitive code (unless its code is designed to cope with such changes) because all cogs share a common clock.

ROM extensions

In addition to the spin interpreter and boot loader , the built-in ROM also contains some data that can be particularly helpful for mathematical calculations and for audio and video applications:

  • a bitmap font set for screen output
  • a logarithmic table (base 2, 2048 entries)
  • an antilogarithmic table (base 2, 2048 entries) for conversions
  • a sine table (16 bit, 2049 entries)

Designs

The Parallax Propeller is available in the designs 40-pin DIP , 44-pin LQFP , or as a particularly space-saving QFN . The DIP design is particularly popular with hobby users because of its easy handling.

External EEPROM

The propeller can load its program from an external serial EEPROM at start-up , after the boot process this memory can be used for other tasks (such as saving measured values).

Open source

The Propeller hardware was released as a Verilog source under the GPL . The ROM code was also published as commented source text. In this way, the entire processor can be reproduced on an FPGA .

The drafts for the P2 are also publicly available so that the chip can be tested in advance and suggestions for improvement can be made.

literature

  • Shane Avery, Chip Gracey, Vern Graner: Programming and customizing the multicore propeller microcontroller - the official guide . Mcgraw-Hill, New York 2010, ISBN 978-0-07-166450-9 (English).

Web links

Manufacturer Pages:

Download Pages:

Related Links:

Individual evidence

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