PowerPC e200

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The PowerPC e200 is a 32-bit RISC - processor core from the PowerPC family. It was designed by Freescale primarily for automotive and industrial systems. The PowerPC e200 is an SoC with a speed of up to 600 MHz. It is therefore suitable for embedded applications.

The e200 is derived from the MPC5xx family and uses the Power ISA v.2.03 and the older Book E specifications. The e200 SoCs follow the MPC55xx and MPC56xx / JPC56x naming scheme.

As of April 2007, Freescale and IPextreme opened the design of the e200 for licensing purposes and manufacturing by other companies.

Freescale and Continental AG are developing a triple-core e200 for electronically supported braking systems in automobiles.

Cores

The e200 family consists of six different cores, starting with very simple to highly complex cores for special applications.

e200z0

The e200z0 is the simplest variant of the e200 core. It has a 4-stage, non- superscalar instruction pipeline that processes instructions linearly ( in-order execution ). There is no MMU or FPU . The e200z0 uses the VLE specification (16-bit version of the 32-bit Book E specification) and thus achieves a code density that is up to 30% higher. A single-channel AMBA bus is used as the bus.

e200z1

The e200z1 has a 4-stage, non- superscalar instruction pipeline with a unit for branch prediction and an 8-entry MMU . There is no FPU . The e200z1 can process all 32 bit Power ISA and VLE commands and uses a two-channel 32 bit AMBA bus.

e200z3

The e200z3 is an e200z1 core expanded by a 16-entry MMU and a SIMD capable FPU . It can also use all commands of the Power ISA and VLE specification but, in contrast to the e200z1, has a two-channel 64 bit AMBA bus.

e200z4

The e200z4 has a 5-stage, 2-fold superscalar instruction pipeline with a unit for branch prediction , a 32-entry MMU , a SIMD- capable FPU and a combined 16 KiB L1 cache ( Von Neumann architecture ). Like its predecessor, it uses all commands of the Power ISA and the VLE specification and is also connected via a two-channel AMBA bus.

e200z6

The e200z6 has a 7-stage non- superscalar instruction pipeline with a unit for branch prediction , a 32-entry MMU , a SIMD- capable FPU and a combined 32 KiB L1 cache . Like its predecessor, it uses all commands of the Power ISA and the VLE specification and is also connected via a two-channel AMBA bus.

e200z7

The e200z7 has a 10-stage, 2-way superscalar instruction pipeline with a unit for branch prediction , a 32-entry MMU , a SIMD- capable FPU and a combined 32 KiB L1 cache . Just like its predecessor, it uses all commands of the Power ISA and the VLE specification and is also connected via a two-channel AMBA bus.

See also

Web links

Individual evidence

  1. ↑ Freescale's e200 Core FamilyBuilt on Power Architecture Technology. P. 2 , accessed on April 28, 2019 (English).
  2. ↑ a b MPC5500 Family. Accessed April 28, 2019 .
  3. ↑ Freescale: News Release ( Memento of October 24, 2007 in the Internet Archive )
  4. ↑ Freescale and Continental Collaborate on Multi-Core 32-bit Microcontrollers for Electronic Braking Systems. November 16, 2007, accessed April 28, 2019 .
  5. ↑ e200z0 Power Architecture Core Reference Manual. Accessed April 28, 2019 .
  6. ↑ e200z1 Power Architecture Core Reference Manual. Accessed April 28, 2019 .
  7. ↑ e200z3 Power Architecture Core Reference Manual. Accessed April 28, 2019 .
  8. ↑ e200z4 Power Architecture Core Reference Manual. Accessed April 28, 2019 .