Subtracter

This article describes the analog circuitry of the subtractor. For the digital circuit of the subtracter see addition circuit

The subtracter is an electronic circuit based on analog technology for measuring electrical potential differences .

In practice, subtractors are implemented from operational amplifiers , negative feedback differential amplifiers or with switched capacitors ( switched capacitor technology ).

Input resistance and quality

When subtractor is the input resistance of particular interest, since when measuring the potential difference there with ${\displaystyle U_{diff}}$

${\displaystyle U_{D}=\phi _{2}-\phi _{1}}$

is important that the potential difference as possible regardless of the difference of the superimposed common-mode voltage with ${\displaystyle U_{Gl}}$

${\displaystyle U_{Gl}={\frac {\phi _{1}+\phi _{2}}{2}}}$

to be measured, since the common-mode voltage can often be larger by a factor of 10 ⁴ or more in practice .

The quality of the common mode rejection ratio (CMRR engl .: - common mode rejection ratio ) is given by the equation ${\displaystyle G}$

${\displaystyle G={\frac {A_{D}}{A_{Gl}}}={\frac {\frac {U_{a}}{U_{D}}}{\frac {U_{D}}{U_{Gl}}}}}$

described. The value of the quality factor of the subtracter must be significantly greater than the ratio of the minimum potential difference to be measured to the maximum common-mode voltage in order to deliver a correct value.

Further problems can arise if the common-mode voltage has its own frequencies, since the frequency and runtime behavior - as well as the changed gain - of the circuit must also be taken into account here.

Structure with operational amplifier

Subtractor from inverter and adder

A subtraction can be traced back to an addition by inverting the signal to be subtracted and then adding the two signals. In the circuit shown in the picture, the input voltage U ₂ at the operational amplifier N _{1 is} inverted. The operational amplifier N ₂ forms an addition circuit and adds the voltage U ₁ to the inverted signal. This results in the relationship for the output voltage

${\displaystyle U_{a}=A_{1}\,U_{2}-A_{2}\,U_{1}}$

where A ₁ and A _{2 represent} the gains of the respective circuits with N ₁ and N _2, respectively. A pure differential gain is obtained if the two gains are chosen to be the same size as the required differential gain

${\displaystyle A_{1}=A_{2}=A_{diff}\to U_{a}=A_{diff}\,\left(U_{2}-U_{1}\right)}$

To calculate the common mode gain (ie the deviation from the ideally pure differential gain) is given in this circuit by

${\displaystyle G={\frac {A_{D}}{A_{Gl}}}}$

By inserting

${\displaystyle U_{2}=U_{Gl}+{\frac {1}{2}}\,U_{D}}$

and

${\displaystyle U_{1}=U_{Gl}-{\frac {1}{2}}\,U_{D}}$

you get

${\displaystyle U_{a}=A_{1}\,U_{2}-A_{2}\,U_{1}}$

${\displaystyle U_{a}=A_{1}\,\left(U_{Gl}+{\frac {1}{2}}\,U_{D}\right)\ -A_{2}\,\left(U_{Gl}-{\frac {1}{2}}\,U_{D}\right)}$

${\displaystyle U_{a}=\left(A_{1}-A_{2}\right)\,U_{Gl}+{\frac {1}{2}}\,\left(A_{1}+A_{2}\right)\,U_{D}}$

${\displaystyle U_{a}=A_{Gl}\,U_{Gl}+A_{D}\,U_{D}}$

Here U _{Gl is} the common mode voltage, A _{Gl is} the common mode gain, U _{D is} the differential voltage and A _{D is} the differential gain .

The common mode rejection results from

${\displaystyle G={\frac {A_{D}}{A_{Gl}}}={\frac {A_{2}+A_{1}}{2\,\left(A_{2}-A_{1}\right)}}}$

In order to achieve maximum common mode rejection, you must

${\displaystyle A_{1}=A_{2}=A_{diff}}$

be valid. This is called the coefficient condition . In this case the following also applies:

${\displaystyle A_{1}=A-{\frac {\Delta A}{2}}}$

${\displaystyle A_{2}=A+{\frac {\Delta A}{2}}}$

By inserting you get

${\displaystyle G={\frac {A_{2}+A_{1}}{2\,\left(A_{2}-A_{1}\right)}}}$

${\displaystyle G={\frac {A+{\frac {\Delta A}{2}}+A-{\frac {\Delta A}{2}}}{2\,\left(A+{\frac {\Delta A}{2}}-(A-{\frac {\Delta A}{2}})\right)}}}$

${\displaystyle G={\frac {A}{\Delta A}}}$

This means that the common mode rejection is equal to the reciprocal of the relative pairing tolerance of the two gains.

Subtracting amplifier

Subtractor with an operational amplifier

A subtracter can also be constructed in a simplified manner with just one operational amplifier. To do this, you connect the signal to be subtracted to the respective inverse connection of the operational amplifier. This makes use of the fact that the operational amplifier only amplifies the differential voltage between its N and P input.

functionality

The equation applies to the adjacent circuit using the superposition theorem

${\displaystyle U_{a}=k_{1}\,U_{1}+k_{2}\,U_{2}}$

The subtraction amplifier works as a reversing amplifier with: ${\displaystyle U_{2}=0}$

${\displaystyle U_{a}=-\alpha _{N}\,U_{1}\to k_{1}=-\alpha _{N}}$

The circuit works as an electrometer amplifier (ie the output is not inverted) with an upstream voltage divider. The potential at the P connection of the operational amplifier results from ${\displaystyle U_{1}=0}$ ${\displaystyle \phi _{P}}$ ${\displaystyle N_{1}}$

${\displaystyle \phi _{P}=U_{2}\,{\frac {R_{P}}{R_{P}+{\frac {R_{P}}{\alpha _{P}}}}}}$

and is reinforced by the factor . Thus: ${\displaystyle 1+\alpha _{N}}$

${\displaystyle U_{a}={\frac {\alpha _{P}}{1+\alpha _{P}}}\,\left(1+\alpha _{N}\right)\,U_{2}}$

Same resistance ratio

In the event that the two resistance ratios are the same, so:

${\displaystyle {\frac {\frac {R_{N}}{\alpha _{N}}}{R_{N}}}={\frac {\frac {R_{P}}{\alpha _{P}}}{R_{P}}}}$

and thus

${\displaystyle \alpha =\alpha _{N}=\alpha _{P}}$

applies, it follows by substituting in the equation above:

${\displaystyle U_{a}=\alpha U_{2}\to k_{2}=\alpha }$

For the output voltage it finally follows:

${\displaystyle U_{a}=\alpha \,\left(U_{2}-U_{1}\right)}$

Unequal resistance ratio

In the event that the two resistance ratios are not the same, the following applies:

${\displaystyle U_{a}={\frac {1+\alpha _{N}}{1+\alpha _{P}}}\,\alpha _{P}\,U_{2}-\alpha _{N}\,U_{1}}$

Common mode rejection

To calculate the common mode rejection, we use the above equations again

${\displaystyle U_{2}=U_{Gl}+{\frac {1}{2}}\,U_{D}}$

and

${\displaystyle U_{1}=U_{Gl}-{\frac {1}{2}}\,U_{D}}$

By inserting you get

${\displaystyle U_{a}={\frac {1+\alpha _{N}}{1+\alpha _{P}}}\,\alpha _{P}\,\left(U_{Gl}+{\frac {1}{2}}\,U_{D}\right)\ -\alpha _{N}\,\left(U_{Gl}-{\frac {1}{2}}\,U_{D}\right)}$

${\displaystyle U_{a}=\left({\frac {1+\alpha _{N}}{1+\alpha _{P}}}\,\alpha _{P}\,-\alpha _{N}\right)\,U_{Gl}+\left({\frac {1+\alpha _{N}}{1+\alpha _{P}}}\,\alpha _{P}\,+\alpha _{N}\right)\,{\frac {1}{2}}\,U_{D}}$

Where

${\displaystyle A_{Gl}={\frac {1+\alpha _{N}}{1+\alpha _{P}}}\,\alpha _{P}\,-\alpha _{N}}$

${\displaystyle A_{D}={\frac {1}{2}}\left({\frac {1+\alpha _{N}}{1+\alpha _{P}}}\,\alpha _{P}\,+\alpha _{N}\right)}$

The common mode rejection results from

${\displaystyle G={\frac {A_{D}}{A_{Gl}}}={\frac {1}{2}}\,{\frac {\left(1+\alpha _{N}\right)\,\alpha _{P}+\left(1+\alpha _{P}\right)\,\alpha _{N}}{\left(1+\alpha _{N}\right)\,\alpha _{P}-\left(1+\alpha _{P}\right)\,\alpha _{N}}}}$

With the coefficient condition

${\displaystyle \alpha _{N}=\alpha -{\frac {\Delta \alpha }{2}}}$

${\displaystyle \alpha _{P}=\alpha +{\frac {\Delta \alpha }{2}}}$

the higher order terms are neglected :

${\displaystyle G\approx \left(1+\alpha \right)\,{\frac {\alpha }{\Delta \alpha }}}$

The common mode rejection is inversely proportional to the tolerance of the resistance ratios when the factor is constant. If the two resistance ratios are the same, the following applies: ${\displaystyle \alpha }$

${\displaystyle G=\infty }$

However, this can only be achieved with an ideal operational amplifier, which does not occur in practice. If the highest possible common-mode rejection is required, the setting is such that the finite common-mode rejection of the operational amplifier is compensated as much as possible. In addition, the common-mode rejection is included when there is a resistance tolerance ${\displaystyle R_{P}}$

${\displaystyle {\frac {\Delta \alpha }{\alpha }}}$

approximately proportional to the set differential gain:

${\displaystyle A_{D}=\alpha }$

Multiple subtractors

Multiple subtractors

The illustration opposite shows the expansion of the subtracter for any number of additions and subtractions. With this circuit, the coefficient condition must be met so that the circuit works correctly. If this is not the case after assigning the coefficients, the voltage 0 is added to or subtracted from the missing coefficient - that is, an additional addition or subtraction input is calculated with a suitable coefficient and connected to ground.

The node rule gives the following for the N input:

${\displaystyle \sum _{i=1}^{m}{\frac {U_{i}-\phi _{N}}{\frac {R_{N}}{\alpha _{i}}}}+{\frac {U_{a}-\phi _{N}}{R_{N}}}=0}$

it follows:

${\displaystyle \sum _{i=1}^{m}{\alpha _{i}\,U_{i}}-\phi _{N}\left(\sum _{i=1}^{m}{\alpha _{i}}+1\right)+U_{a}=0}$

The node rule also provides for the P input:

${\displaystyle \sum _{i=1}^{n}{\alpha '_{i}\,U'_{i}}-\phi _{P}\left(\sum _{i=1}^{n}{\alpha '_{i}}+1\right)=0}$

If the additional conditions

${\displaystyle \phi _{N}=\phi _{P}}$

and

${\displaystyle \sum _{i=1}^{m}{\alpha _{i}}=\sum _{i=1}^{n}{\alpha '_{i}}}$

are fulfilled, the equation follows by subtracting the two equations

${\displaystyle U_{a}=\sum _{i=1}^{n}{\alpha '_{i}\,U'_{i}}-\sum _{i=1}^{m}{\alpha _{i}\,U_{i}}}$

Subtractor with high impedance inputs

Subtracter from subtracting amplifier with impedance converters

The structure of the subtractor with high-impedance inputs is essentially based on the subtractor amplifier , but offers additional voltage followers at the inputs so that the potentials to be measured are not burdened with the input resistance of the subtractor. In addition, a higher common mode rejection can be achieved if the voltage gain is shifted to the impedance converter and the gain 1 is set on the subtractor.

The following equation applies to the subtraction amplifier with impedance converters shown in the picture:

${\displaystyle U_{a}=\left(\phi _{2}-\phi _{1}\right)\,{\frac {R_{2}}{R_{1}}}}$

Symmetrical electrometer subtracter

Electrometer subtractor

A special case of this type is the (symmetrical) electrometer subtractor , in which an additional resistor is connected between the two impedance converters . This type of circuit is commonly known as an instrumentation amplifier , instrumentation amplifier , or instrumentation amplifier . Instrumentation Amplifier , called InAmp for short . This circuit is a particularly precise operational amplifier circuit with very high-resistance (typ. 1 GΩ) inputs, particularly high common-mode rejection and low input offset voltage. ${\displaystyle R_{r}}$

The resistor makes the differential gain adjustable. In the two operational amplifiers at the input as a voltage follower, which the subtracting amplifier with impedance converters without equal. The potential difference occurs at the resistor . This means: ${\displaystyle R_{r}}$ ${\displaystyle R_{r}=\infty }$ ${\displaystyle R_{r}}$ ${\displaystyle R_{r}}$ ${\displaystyle \phi _{2}-\phi _{1}}$

${\displaystyle \phi '_{2}-\phi '_{1}=\left(\phi _{2}-\phi _{1}\right)\,\left(1+{\frac {2\,R_{1}}{R_{r}}}\right)}$

The difference is transferred to the output. ${\displaystyle \phi '_{2}-\phi '_{1}}$

The following applies to pure common-mode control

${\displaystyle \phi _{1}=\phi _{2}=\phi '_{1}=\phi '_{2}=\phi _{Gl}}$

whereby the common mode gain always has a factor of 1. This results in the relationship for common-mode rejection

${\displaystyle G=\left(1+{\frac {2\,R_{1}}{R_{r}}}\right)\,{\frac {2\,\alpha }{\Delta \alpha }}}$

where the factor represents the relative pairing tolerance of the resistors . ${\displaystyle {\frac {2\,\alpha }{\Delta \alpha }}}$ ${\displaystyle R_{2}}$

see main article: Instrumentation Amplifiers

Asymmetric electrometer subtractor

Due to the asymmetrical structure of the electrometer subtractor, the operational amplifier at the output can be omitted.

Asymmetric electrometer subtractor

The asymmetrical electrometer subtractor shown in the first picture amplifies the input signal at the operational amplifier with the amplification ${\displaystyle U_{1}}$ ${\displaystyle N_{1}}$

${\displaystyle 1+{\frac {R_{1}}{R_{2}}}}$

and the input signal with the operational amplifier with the gain ${\displaystyle U_{2}}$ ${\displaystyle N_{2}}$

${\displaystyle 1+{\frac {R_{2}}{R_{1}}}}$.

In addition, the potential induced in the flow point is added to the weighting ${\displaystyle \phi '_{1}}$

${\displaystyle -{\frac {R_{2}}{R_{1}}}}$.

In terms of amount, the two input voltages are increased by the factor

${\displaystyle 1+{\frac {R_{2}}{R_{1}}}}$

reinforced. Therefore results for the output voltage

${\displaystyle U_{a}=\left(\phi _{2}-\phi _{1}\right)\,\left(1+{\frac {R_{2}}{R_{1}}}\right)}$

---

As shown in the second picture, the use of an additional (adjustable) resistor between the potentials and the gain of the circuit can be adjusted. The equation applies to the output voltage ${\displaystyle R_{r}}$ ${\displaystyle \phi _{1}}$ ${\displaystyle \phi _{2}}$

${\displaystyle U_{a}=\left(\phi _{2}-\phi _{1}\right)\,2\,\left(1+{\frac {R_{2}}{R_{1}}}\right)}$

---

The circuit shown in the third picture can also be used for applications in which only one high-impedance input is required. This only requires a single operational amplifier. However, the gain of is always greater than that of , which further restricts the possible uses, but which does not represent a disadvantage, for example, in the amplification and zero point shift of sensor signals. The equation applies to the output voltage ${\displaystyle U_{2}}$ ${\displaystyle U_{1}}$

${\displaystyle U_{a}=U_{2}\,\left(1+{\frac {R_{N}}{R_{1}}}+{\frac {R_{N}}{R_{2}}}\right)-U_{1}\,{\frac {R_{N}}{R_{1}}}}$

In addition, omitting ( ) results in a conventional amplifier. If one also sets this, the relationship applies to the output voltage ${\displaystyle R_{2}}$ ${\displaystyle R_{2}=\infty }$ ${\displaystyle R_{1}=R_{N}}$

${\displaystyle U_{a}=2\,U_{2}-U_{1}}$

High voltage subtractor

High voltage subtractor

High- impedance inputs are also required for subtracting high voltages. However, since high attenuation is required in order to reduce the high voltage at the input to a low voltage at the output, one chooses . Because the two resistors and thus the inputs are very high-resistance, the impedance amplifiers at the input can be omitted. At the same time, the voltage divider, consisting of and, is used to reduce the voltage so far that no high-voltage operational amplifier is required. ${\displaystyle R_{1}\gg R_{2}}$ ${\displaystyle R_{1}}$ ${\displaystyle R_{1}}$ ${\displaystyle R_{2}}$

The high-voltage subtractor shown in the first figure has the disadvantage that the difference signal is also very much attenuated. The following applies to the gain in the first circuit:

${\displaystyle A={\frac {R_{2}}{R_{1}}}\ll 1}$

In order to achieve the greatest possible modulation with small voltage differences, an additional amplifier must be used at the output, which, however, worsens the signal-to-noise ratio .

To avoid this problem, one can use the high voltage subtractor with adjustable gain . With this circuit, the attenuation of the high input voltages and the amplification of the differential voltage can be dimensioned separately. The resistors and determine the gain, while the resistors only affect the common mode level. The high-voltage subtracter shown in the figure with adjustable gain corresponds to the INA 148 from Burr Brown and has a gain of 1 for the voltage difference. ${\displaystyle R_{1}}$ ${\displaystyle R_{2}}$ ${\displaystyle R_{3}}$

The disadvantage of the high-voltage subtractor with adjustable gain is that the two resistors attenuate the input signals of the operational amplifier. This reduces the loop gain and consequently also the bandwidth of the circuit. In addition, the offset voltage and the offset voltage drift of the operational amplifier are amplified. This means that much better operational amplifiers are required in this circuit. In addition, components with a very low tolerance are required for the two resistors. The resistances and at the non-inverting input are not combined in order to ensure the lowest possible synchronization tolerance. ${\displaystyle R_{3}}$ ${\displaystyle R_{3}}$ ${\displaystyle R_{2}}$ ${\displaystyle R_{3}}$

Structure with differential amplifier

Electrometer subtractor with negative feedback differential amplifiers

The manual dimensioning of the current feedback can be the difference gain of the differential amplifier set. In addition, a high level of common mode rejection can be achieved in the differential amplifier by using a constant current source at the emitter. Such a circuit is shown in the adjacent figure.

The transistors V ₁ and V ₂ form the actual differential amplifier at the inputs of the circuit and are fed back via the resistor R _G. The difference in the collector currents is converted into the output voltage at the operational amplifier N ₁ .

With the second differential amplifier - consisting of V ₃ and V ₄  - an equally large current difference is formed.

${\displaystyle \Delta I_{C}={\frac {V_{2}-V_{1}}{R_{G}}}={\frac {V_{4}-V_{3}}{R_{S}}}}$

This compensates for the current difference so that the collector currents of V ₁ and V ₂ always have the same current as the current sources (I ₁ ). This is achieved in that the operational amplifier N _{1 is} fed back to V ₄ .

The following applies to the output voltage : ${\displaystyle U_{a}}$

${\displaystyle U_{a}=\left(\phi _{2}-\phi _{1}\right)\,\left(1+{\frac {R_{2}}{R_{1}}}\right)\,{\frac {R_{S}}{R_{G}}}}$

The resistors R ₁ and R _{2 are} already fixed in prefabricated integrated circuits . The gain of the circuit is in this case via the resistors R _G and R _S is set. The advantage, however, is that the strength of the common-mode rejection does not depend on the pairing tolerance of R _G and R _S , which means that one does not have to rely on (laser-trimmed) thin-film resistors specially adapted to the individual circuit.

Structure in SC technology

Switched capacitor technology subtracter

The principle of a subtracter in switched capacitor technology is based on the fact that a storage capacitor C _{S is} first charged to the voltage to be measured. The electrical charge of this capacitor is then transferred to a second holding capacitor C _{H which is} grounded on one side to ground . After several switching cycles and sufficient charging and recharging times, the differential voltage is present on the two capacitors.

${\displaystyle U_{H}=U_{S}=U_{D}=\phi _{2}-\phi _{1}}$

Since the holding capacitor is connected to ground, no common-mode voltage occurs, as a result of which the voltage on the second capacitor can be amplified via a simple electrometer amplifier without additional formation of a difference. This enables a very high level of common mode rejection to be achieved.

The accuracy of the difference formation is almost exclusively determined by the stray capacitances of the switches. In order to let this be relatively small, the capacitors C _S and C _H preferably selected to be large (about 1 μ F ).

With the integrated LTC1043 switch from Linear Technology , for example, common-mode rejection of 120  dB can be achieved up to a frequency of 20 k Hz (ie the common-mode component is reduced by a factor of 10 ⁶ ).

The bandwidth of the circuit is reduced by three low-pass filters:

1. Charging the storage capacitor
2. Charge transfer from the storage capacitor to the holding capacitor
3. Bandwidth of the amplifier

Charging the storage capacitor

The charging time of the capacitor is determined by the capacitance of the storage capacitor and the resistance of the switches (2 · 240  Ω for the LTC1043) plus the internal resistance of the source.

Charge transfer from the storage capacitor to the holding capacitor

Before the first charge transfer is

${\displaystyle U_{H}=0}$,

after the first charge transfer is

${\displaystyle U_{H}={\frac {1}{2}}\,U_{D}}$,

after the second charge transfer is

${\displaystyle U_{H}={\frac {3}{4}}\,U_{D}}$,

after the third charge transfer is

${\displaystyle U_{H}={\frac {7}{8}}\,U_{D}}$,

etc. The resulting time constant therefore corresponds to approximately two switching cycles. In order to keep parasitic charges from the switching process low, switching frequencies of 500 Hz are used. Therefore, only low-frequency differential signals can be processed with this circuit.

Bandwidth of the amplifier

The bandwidth of the amplifier may also reduce the usable bandwidth. The bandwidth of the amplifier is limited via the additional capacitor at R ₂ . In practice, this capacitor is chosen so that the bandwidth is limited to the frequency range to be measured (e.g. up to 50 Hz) in order to filter higher-frequency signals and thus keep noise and interference from switching at the output low.

Subtractor modules

Legend for the adjacent table

Type	construction
InAmp	Symmetrical Electrometer Subtractor (Instrumentation Amplifier)
Diff	Structure with differential amplifier
Asym	Asymmetrical structure
AsymS	Asymmetrical structure; adjustable
HVSub	High voltage subtractor
HVSubS	High voltage subtractor; Adjustable gain
Note: Abbreviations are chosen arbitrarily

Integrated subtractors

Manufacturer	ID	A.	I e	U offset	Type	special features
Analog Devices	AD620	1… 1k	0.5 nA	50 µV	Diff	cheap price
	AD621	10, 100	0.5 nA	50 µV	Diff
	AD623	1… 1k	17 nA	100 µV	InAmp	Rail-to-Rail Offset (RRO)
	AD624	1… 1k	25 nA	25 µV	Asym	precise
	AD629	1	2.5 µA V −1	200 µV	HVSubS	U GL = ± 270 V
Linear Technology	LT1101	10, 100	6 nA	50 µV	Asym	P b = 0.5 mW
	LT1102	10, 100	10 pA	200 µV		${\displaystyle {\frac {\Delta U_{a}}{\Delta t}}=25\,{\frac {\mathrm {V} }{\mathrm {\mu s} }}}$
	LT1167	1… 10k	100 pA	20 µV	InAmp	precise
	LTC1100	100	25 pA	2 µV	Asym	Autozero function
National	CLC522	1… 10	20 µA	25 µV	Diff	${\displaystyle {\frac {\Delta U_{a}}{\Delta t}}=2\,{\frac {\mathrm {kV} }{\mathrm {\mu s} }}}$
Texas Instruments	INA103	1 ... 100	2.5 µA	50 µV	InAmp	${\displaystyle U_{r}=1\,{\frac {\mathrm {nV} }{\sqrt {\mathrm {Hz} }}}}$
	INA105	1	20 µA V −1	50 µV	HVSub
	INA106	10	50 µA V −1	50 µV
	INA110	1… 5k	20 pA	50 µV	InAmp	${\displaystyle {\frac {\Delta U_{a}}{\Delta t}}=17\,{\frac {\mathrm {V} }{\mathrm {\mu s} }}}$
	INA114	1… 1k	1 nA	25 µV		precise;
	INA116	1… 1k	3 fA	2 mV		I B ≈ 3 fA
	INA118	1… 10k	1 nA	20 µV		I B = 0.4 mA
	INA121	1… 10k	4 pA	200 µV
	INA122	5… 10k	10 nA	100 µV	AsymS	I B = 60 µA
	INA131	100	1 nA	25 µV	InAmp	precise; cheap price
	INA148	1	1 µA V −1	1 mV	HVSubS	U GL = ± 200 V
	INA2141	10, 100	2 nA	20 µV	InAmp	2 subtractors in the IC
	PGA204	1… 1k	2 nA	50 µV		Gain digitally adjustable
	PGA207	1… 10	2 pA	1 V

literature

• Ulrich Tietze, Christoph Schenk, Eberhard Gamm: Semiconductor circuit technology. 12th edition. Springer, 2002, ISBN 3-540-42849-6 .
• Walter G. Jung (Ed.): OP AMP Applications. Company publication Analog Devices, 2002, ISBN 0-916550-26-5 .

See also

• Summing amplifier
• Isolation amplifier

Web links

• INA 148

footnote

1. ↑ This term is misleading because it is also used for electrical musical instruments, see guitar amplifier .