Transactional storage
Transactional memory is a concept in computer science for parallel computation units that access shared memory areas , such as B. threads or multiprocessor systems . The aim is to increase the execution speed compared to previous synchronization methods, and to solve the synchronization difficulties that arise with parallel software, especially when it consists of several independently developed components. Transactional storage can be implemented either completely as software (STM), as hardware (HTM) or with hardware support (hybrid HTM).
Existing systems with hardware-supported transactional storage were initially only available as research prototypes, for example the ATLAS system from Stanford University. In the meantime, however, the systems are ready for series production. The first processor with transactional memory was IBM Blue Gene / Q . Intel announced in February 2012 that it would equip its next generation of processors, the Haswell, with transactional memory.
The concept comes from Maurice Herlihy and Eliot Moss .
concept
With parallel programming, errors can quickly creep in, which can lead to blockages within the system (so-called deadlocks ). Transactional storage should fundamentally solve this problem and thereby considerably simplify the parallelization of software.
The idea of transactional storage comes from the architecture of database systems . A transaction bundles commands that access common resources. If two transactions want to access the same resource, one of the two transactions is canceled. This releases the occupied resources and resets all changes made ( rollback ). An intelligent management mechanism, the heart of transactional storage, decides which transaction is canceled.
Availability
So far, there have only been software-based methods for implementing transactional memory ( software transactional memory , STM ), but these are slower than hardware-based methods. The additional effort that arises with the programs that use STM is too great to be able to compete with systems with conventional synchronization mechanisms.
The computer chip manufacturer Intel demonstrated the speed advantage of transactional memory for the first time at a developer conference in early 2006, but only using a software simulation. With selected CPUs of the current Haswell architecture, Intel offers the concept under the name Transactional Synchronization Extensions as an x86 architecture extension.
At the ISSCC 2008 Sun Microsystems presented details of a 16-core Sparc processor with hardware-supported transactional memory with the ROCK processor . However, its development was stopped with the acquisition of Sun by Oracle in 2010.
Research models
- UTM - Unbounded Transactional Memory
- LTM - Large Transactional Memory
- VTM - Virtual Transactional Memory
- LogTM - Log-based Transactional Memory
- TCC - Transactional Memory Coherence and Consistency
literature
- Maurice Herlihy , J. Eliot B. Moss: Transactional memory: Architectural support for lock-free data structures . In: Proceedings of the 20th International Symposium on Computer Architecture (ISCA) . 1993, p. 289-300 ( cs.brown.edu [PDF]).
- JR Larus, R. Rajwar: Transactional Memory . Morgan & Claypool, 2006.
- Calin Cascaval, Colin Blundell, Maged Michael, Harold W. Cain, Peng Wu, Stefanie Chiras, Siddhartha Chatterjee: Software Transactional Memory: Why Is It Only a Research Toy? In: Queue . tape 5 , no. 6 . ACM, September 2008, ISSN 1542-7730 , p. 40: 46-40: 58 , doi : 10.1145 / 1454456.1454466 ( acm.org [accessed November 2, 2015]).
Individual evidence
- ↑ TCC prototypes ( Memento of the original from March 28, 2009 in the Internet Archive ) Info: The archive link was automatically inserted and not yet checked. Please check the original and archive link according to the instructions and then remove this notice.
- ↑ heise.de
- ^ Rock (processor) in the English language Wikipedia
- ↑ opensparc.net (PDF)
- ↑ Special Report: Can that guy in Ironman 2 whip IBM in real life? . Reuters . May 12, 2010. Retrieved May 21, 2011.
- ↑ cs.wisc.edu
