Transmeta Crusoe

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Crusoe is a family of x86 -compatible CPUs from Transmeta , which were used especially for energy-saving notebooks and similar computers.

Transmeta developed a new concept to make the x86-different CPU x86-compatible: A software solution called code morphing emulates an x86 CPU in real time . Since emulations are usually quite inefficient, the Transmeta software continuously optimizes the emulation of the running programs during runtime . The processor itself is a 128-bit VLIW processor, which has a much simpler structure than a normal x86 CPU from Intel or AMD and thus requires significantly less power or produces significantly less waste heat.

In principle, any CPU architecture can be simulated with the code morphing software. The Crusoe was limited to x86 commands including MMX . In theory it would also be possible to use SSE or 3DNow! to emulate.

The successor to the Crusoe is the Efficeon .

Model data

TM3200

Was initially referred to as TM3120

  • L1 cache: 32 + 64 KB (data + instructions)
  • MMX
  • VLIW with code morphing technology
  • Northbridge integrated in the CPU
  • Packaging:
    • 474 pin CBGA
  • Release DATE: January 2000
  • Manufacturing technology: 220 nm at IBM
  • Clock rates: 333, 366 and 400 MHz

TM5400

  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 256 KB with processor clock
  • MMX , LongRun
  • VLIW with code morphing technology
  • Northbridge integrated in the CPU
  • Packaging:
    • 474 pin CBGA
  • Release DATE: January 2000
  • Manufacturing technology: 180 nm at IBM
  • The size: 73 or 88 mm² with 36.8 million transistors
  • Clock rates: 500 - 700 MHz

TM5500

  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 256 KB with processor clock
  • MMX , LongRun
  • VLIW with code morphing technology
  • Northbridge integrated in the CPU
  • Packaging:
    • 474 pin CBGA
  • Release DATE: June 2001
  • Manufacturing technology: 130 nm at TSMC
  • The size: 55 mm² with 36.8 million transistors
  • Clock rates: 300 - 800 MHz

TM5600

Crusoe TM5600.
  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 512 KB with processor clock
  • MMX , LongRun
  • VLIW with code morphing technology
  • Northbridge integrated in the CPU
  • Packaging:
    • 474 pin CBGA
  • Release DATE: October 2000
  • Manufacturing technology: 180 nm at IBM
  • The size: 88 mm² with 36.8 million transistors
  • Clock rates: 300 - 666 MHz

TM5700

  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 256 KB with processor clock
  • MMX , LongRun
  • VLIW with code morphing technology
  • Northbridge integrated in the CPU
  • Packaging:
    • 399 pin OBGA
  • Release DATE: January 2004
  • Manufacturing technology: 130 nm at TSMC
  • The size: 55 mm² with 36.8 million transistors
  • Clock rates: 667 MHz

TM5800

Transmeta Crusoe TM5800.
  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 512 KB with processor clock
  • MMX , LongRun
  • VLIW with code morphing technology
  • Northbridge integrated in the CPU
  • Packaging:
    • 474 pin CBGA
  • Release DATE: June 2001
  • Manufacturing technology: 130 nm at TSMC
  • The size: 55 mm² with 36.8 million transistors
  • Clock rates: 300 - 1000 MHz

TM5900

  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 512 KB with processor clock
  • MMX , LongRun
  • VLIW with code morphing technology
  • Northbridge integrated in the CPU
  • Packaging:
    • 399 pin OBGA
  • Release DATE: January 2004
  • Manufacturing technology: 130 nm at TSMC
  • The size: 55 mm² with 36.8 million transistors
  • Clock rates: 800 - 1000 MHz

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