Sub-threshold effect

The sub-threshold effect ( English subthreshold effect ) describes the observation of a MOS field effect transistor (MOSFET) that even without inversion channel below the threshold voltage U _th a small drain current can flow. This current is also sub-threshold leakage current ( English subthreshold leakage current ) mentioned, which indicates that this is an undesired current flow in the channel direction, of an increase in the energy consumption of the integrated circuit leads (see also general leakage current ).

The MOSFET in digital circuits

Schematic structure of a lateral n-channel MOSFET in planar technology

A normal MOS transistor (see figure) essentially consists of two electrodes for contacting the semiconductor ( drain and source ) and an additional, electrically isolated control electrode ( gate ). If there are no voltages, the transistor is in thermodynamic equilibrium and the charge carriers essentially only move through diffusion ; Diffusion is understood to be a physical equalization process in which there is an overall flow of particles from a high to a low concentration, but individual particles can also move in opposite directions. Another cause of particle transport is thermionic emission . Starting from a normally-off n-channel MOSFET, in the ideal case no current flows between the drain and source as long as the gate-source voltage is lower than the threshold voltage . When the gate-source voltage increases (it applies ), more and more electrons collect at the interface of gate insulator and semiconductor (between drain and source) until inversion occurs and a conductive channel is formed. ${\displaystyle U_{\mathrm {gs} }}$ ${\displaystyle U_{\mathrm {th} }}$ ${\displaystyle U_{\mathrm {gs} }<U_{\mathrm {th} }}$

In digital circuits there are only the two logical signals '0' and '1' which are represented by the voltage level GND (= 0 V) ​​and VDD ( operating voltage ). Thus, in ideal digital circuits, there are only two states for the MOS transistors:

1. The MOS transistor is blocked, i.e. In other words , there is no channel between drain and source and thus no current flow between drain and source is possible
2. The MOS transistor is conductive, i.e. This means that there is a channel between the drain and the source and thus a current flow between the drain and the source is also possible.

Area of ​​weak inversion in analog MOS circuits

In analog circuits, the gate-source voltage can also assume values ​​between GND and VDD. The voltage range in which the gate-source voltage is between the flat band voltage and the threshold voltage is known as the subthreshold region (also known as the subthreshold region ). In this area, the area between drain and source is in so-called weak inversion (engl. Weak inversion ) and there is a small number of free charge carriers before. In the sub-threshold range, the charge carriers move mainly by diffusion instead of drifting caused by a source-drain voltage. In analog circuits, this source-drain current is also known as the subthreshold current , also known as weak inversion current . This shows that, unlike digital circuits, it is mostly desirable. Furthermore, the source-drain current can be calculated approximately like the collector current of a bipolar transistor with a homogeneously doped base in this region . The existing layer structure (source, substrate, drain) works like an npn bipolar transistor. An exponential relationship is obtained between the drain current and the gate-source voltage (below the threshold voltage): ${\displaystyle U_{\mathrm {gs} }}$ ${\displaystyle I_{D}}$

${\displaystyle I_{D}\sim \mathrm {e} ^{\frac {q(V_{gs}-V_{th})}{k_{B}T}}}$

For this reason, the sub-threshold range of MOSFETs is in part important for analog circuits that operate at low voltage or low power.

In recent years, this technology has also been used increasingly for digital circuits. The goals here are either very low power consumption (e.g. radio nodes for sensor networks) or high performance due to the sometimes very short delay times that can be achieved. The main design challenges here are the strong influences of manufacturing fluctuations and the highly non-linear dependencies of the cell delay time and power consumption of the input signal rise and load capacity.

Significance with advancing miniaturization

A characteristic size of a MOS field effect transistor is the length of the gate. It is true that in digital circuits that were implemented in MOS technologies with gate lengths greater than 0.25 µm, virtually no sub-threshold leakage current occurs. However, if the gate length is shorter, the sub-threshold leakage current increases exponentially. This unwanted current flow leads to an increase in the energy consumption of the integrated circuits. Studies predict that in current and future processors, leakage currents account for up to half of the total energy consumption.

As the structure size of the MOS transistors decreases, the operating voltage is also reduced. This is based on the great influence of the operating voltage on the energy consumption of the integrated circuits. However, this reduces the switching speed of the MOS transistors and thus the performance of the integrated circuits. To counteract this trend, the threshold voltage is also reduced at the same time . However, this means that the MOS transistors can no longer be completely blocked with the aid of the digital signals GND (NMOS transistor) or VDD (PMOS transistor). The area between drain and source is in this case in weak inversion and the application of an electric field (i.e. the drain-source voltage is greater than 0 V) ​​results in a diffusion current between the drain and source . In addition, the influence of the thermionic emission also increases . The effects resulting from this current flow (engl. In digital circuits as sub-threshold leakage current subthreshold leakage current ) , respectively. ${\displaystyle U_{\mathrm {th} }}$ ${\displaystyle U_{\mathrm {ds} }}$ ${\displaystyle I_{\mathrm {sub} }}$

The threshold voltage has a significant influence on the sub-threshold leakage current . The lower this is, the greater the number of free charge carriers within the weak inversion layer. This leads to an exponential increase in the diffusion current, comparable to the current flow of a forward-biased diode. Therefore, the calculation of the drain current with the usual equations in the pinch-off area is no longer correct. ${\displaystyle U_{\mathrm {th} }}$

${\displaystyle I_{sub}}$ can be determined with:

${\displaystyle I_{\rm {sub}}=k\,{\frac {W_{\rm {eff}}}{L_{\rm {eff}}}}\,\left(1-\mathrm {e} ^{-{\frac {V_{\mathrm {ds} }}{\phi _{\mathrm {T} }}}}\right)\,\mathrm {e} ^{\frac {V_{\rm {gs}}-V_{\rm {th}}}{\phi _{\mathrm {T} }\,s_{\rm {th}}}}}$

With

${\displaystyle k=\mu _{\mathrm {0} }\,\phi _{\mathrm {T} }^{2}\,{\sqrt {\frac {N_{\rm {D}}q\,\epsilon _{\rm {Si}}}{2\phi _{\rm {sub}}}}}}$

and the temperature stress

${\displaystyle \phi _{\mathrm {T} }={\frac {k_{\mathrm {B} }\,T}{q}}}$

Meaning of the symbols:

• ${\displaystyle \mu _{\rm {0}}}$... load carrier mobility
• ${\displaystyle W_{\rm {eff}}}$... effective gate width
• ${\displaystyle L_{\rm {eff}}}$... effective gate length
• ${\displaystyle N_{\rm {D}}}$... doping in the channel area
• ${\displaystyle q}$... elementary charge or charge of the charge carriers (1.602 · 10 ⁻¹⁹  C)
• ${\displaystyle \epsilon _{\rm {Si}}}$... dielectric constant of silicon
• ${\displaystyle \phi _{\rm {sub}}}$ ... surface potential of the substrate
• ${\displaystyle k_{\rm {B}}}$... Boltzmann constant (1.381 · 10 ⁻²³  J / K)
• ${\displaystyle T}$... temperature
• ${\displaystyle s_{\rm {th}}}$... Unterschwellenhub (Engl. Subthreshold swing )

The effective gate length and the effective gate width are less than the physical dimensions of the transistor. The reduction is based on the so-called short channel effects , which occur in MOS technologies with gate lengths below 0.25 µm. ${\displaystyle L_{\mathrm {eff} }}$ ${\displaystyle W_{\mathrm {eff} }}$ ${\displaystyle L}$

The drain current-gate voltage characteristic curve for fixed drain, source and bulk voltages corresponds approximately to a logarithmically linear behavior. The slope, ie, the slope of the line with logarithmic scaling drain current is the subthreshold slope (Engl. Subthreshold slope ).

The subthreshold swing is therefore the reciprocal of the subthreshold swing ( S _s-th ), which is calculated as:

${\displaystyle S_{s-th}=\ln(10){kT \over q}\left(1+{C_{d} \over C_{ox}}\right)}$

with the capacity of the depletion zone , the gate oxide capacity and the thermal voltage . ${\displaystyle C_{d}}$ ${\displaystyle C_{ox}}$ ${\displaystyle {kT \over q}}$

The small sub-threshold swing of a conventional transistor can be found under the conditions and / or . It results (also known as the thermionic limit) and corresponds to approximately 60 millivolts per decade at room temperature (a gate voltage change by a factor of 10). A typical value for the sub-threshold steepness of a scaled-down MOSFET at room temperature is approx. 70 millivolts per decade, i.e. somewhat lower due to short channel effects. ${\displaystyle \textstyle {C_{d}}\rightarrow 0}$ ${\displaystyle \textstyle {C_{ox}}\rightarrow \infty }$ ${\displaystyle S_{s-th,\min }=\ln(10){kT \over q}}$

A component with a large sub-threshold steepness has a faster transition between the off-state (low current) and on-state (high current).

Web links

• Optimization of Ultra-Low-Power CMOS Transistors ; Michael Stockinger, 2000.

literature

• SM Sze: Semiconductor devices. 2nd Edition. Wiley & Sons, 2002, ISBN 0-471-33372-7 .
• TA Fjeldly, M. Shur: Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs. In: IEEE Transactions on Electron Devices. No. 40, 1993, pp. 137-145.

Individual evidence

1. ↑ Ulrich Tietze, Christoph Schenk, Eberhard Gamm: Semiconductor circuit technology . 11., completely reworked. and exp. Edition. Springer, Berlin / Heidelberg 1999, ISBN 3-540-64192-0 , pp. 223 .
2. ↑ B. Van Zeghbroeck: 3.4.2 Thermionic emission. In: Principles of Semiconductor Devices. 2004, accessed on July 4, 2020 . 
3. ↑ B. Van Zeghbroeck: 3.2.2 Flatband diagram and built-in potential. In: Principles of Semiconductor Devices. 2004, accessed on July 4, 2020 . 
4. ^ ^{A b} N. Weste, D. Harris: CMOS VLSI Design - A Circuits and Systems Perspective. 3. Edition. Addison-Wesley, 2005, ISBN 0-321-14901-7 .
5. ↑ YS Borkar: VLSI Design Challenges for Gigascale Integration. In: 18th Conference on VLSI Design , Kolkata, India, 2005
6. ↑ ITRS - International Technology Roadmap for Semiconductors 2006 Update. Technical report, 2006.
7. ↑ Dimitrios Soudris, Christian Piguet, Costas Goutis (eds.): Designing CMOS Circuits for Low Power . Springer, Berlin 2002, ISBN 1-4020-7234-1 .
8. ↑ Simon M. Sze, Kwok K. Ng: Physics of Semiconductor Devices . 3. Edition. John Wiley & Sons, Hoboken, NJ 2006, ISBN 0-471-14323-5 , pp. 315 . .
9. ↑ C. Auth et al. a .: A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors . In: 2012 Symposium on VLSI Technology (VLSIT) . 2012, ISBN 978-1-4673-0847-2 , pp. 131-132 , doi : 10.1109 / VLSIT.2012.6242496 .