Value change dump
Value Change Dump ( VCD ) is an ASCII -based format for so-called dump files that are generated, for example, by an EDA tool. The standard VCD format with tetravalent logic has been linked to the 1995 Verilog - hardware description language as IEEE approved standard 1364-1995. An expansion of the VCD format six years later in the form of the IEEE standard 1364–2001 also supports the recording of signal strength and direction. The simple and compact structure of the VCD format made it a universal and unavoidable file format even for non-Verilog tools, such as. As VHDL , the free simulator GHDL and various kernel - Tracer .
structure
The VCD file has a header that contains a time stamp, the simulator version number and a time scale definition. There is also a variable definition area and a value change area. The areas are not explicitly separated from one another, but can be differentiated using the keywords .
The variable definition area contains display information and the list of the instantiated signals. Any compact ASCII identifier is assigned to each variable for use in the change area. The display type setting follows the Verilog concept and includes the types module , task , function and fork .
The change area contains a series of time-ordered value changes of the signals of the simulation model.
syntax
VCD keywords are marked with a $ . Basically, keywords introduce a section that is terminated by the keyword $ end .
Example:
$timescale 1 ns $end
An example of a VCD file:
$timescale 1ps $end $scope module logic $end $var wire 8 # data $end $var wire 1 $ data_valid $end $var wire 1 % en $end $var wire 1 & rx_en $end $var wire 1 ' tx_en $end $var wire 1 ( empty $end $var wire 1 ) underrun $end $upscope $end $enddefinitions $end #0 b10000001 # 0$ 1% 0& 1' 0( 0) #2211 0' #2296 b0 # 1$ #2302 0$ #2303
The code above defines seven signals using $ var :
$var Typ Bitbreite ID Name
The ID is then used in the modification part for identification, which begins after the keyword $ enddefinitions $ end . The range is based on time stamps (S) that begin with # and define the simulation time (t) using the scale definition (D) and , e.g. B. D = 1 ns, S = 500 → t = 500 ns.
After each time stamp, only the values and the assigned signal are listed which change at the time of the stamp.
The change is described by the following line:
Neuer_Wert ID
However, the space or the space must be omitted (see code example above).
All VCD tokens , on the other hand, are separated by a space.
literature
- IEEE Computer Society (Ed.): 1364-2001 IEEE Standard Verilog Hardware Description Language . Official standard. 2001, ISBN 0-7381-2826-0 , doi : 10.1109 / IEEESTD.2001.93352 (English, ieeexplore.ieee.org [accessed August 25, 2010]).