GgNMOS
Under the designation ggNMOS , for English gate-ground-NMOS or English grounded gate NMOS is in the microelectronics understood a conventional protection circuit, which the harmful effects of external electrostatic discharge (ESD) in integrated circuits is limited (IC). The name is derived from the N-channel metal-oxide-semiconductor field-effect transistor (N-MOSFET, NMOS) used as a protective element , which is provided directly on the die at every externally accessible connection pin. The high electrical voltage that occurs during ESD is diverted by the ggNMOS against the reference potential and thus rendered harmless. Without a protective element, the discharge would cause irreversible damage and destruction inside the integrated circuits.
construction
The N-MOSFET is connected in this circuit, as shown in the adjacent simplified sectional illustration, so that its source and gate terminals are connected to ground potential. The drain connection is connected to the connection pin of the integrated circuit to be protected. Since the gate and source are at the same ground potential, the ggNMOS is blocked during normal operation, the N-channel located under the gate oxide is high-resistance and therefore has no influence on the integrated circuit and its function.
In addition to the eponymous N-MOSFET is formed by the structure of the impurity regions, n- and p- doped in the p-substrate of the regions in the semiconductor, semiconductor , a parasitic bipolar transistor (NPN). The base connection (B) is connected to the p-substrate of the semiconductor, the collector connection to the drain connection and the emitter to the source connection. If there is an ESD with a correspondingly high voltage, a reversible avalanche breakdown occurs on the bipolar transistor in the collector-base path . This current through the base causes a voltage drop at the parasitic base resistance, marked in the sketch with R SUB and primarily formed by the resistance in the p-semiconductor substrate, which opens the bipolar transistor in the collector-emitter path and diverts the electrostatic charge to the reference potential. This protective function is also given when the integrated circuit is de-energized, for example during storage or assembly .
The actual protective function does not result in the ggNMOS thus directly through which, in the production of manufactured with standard manufacturing processes in the semiconductor substrate N-channel MOSFET, but it is realized by the structure of the MOSFET structure in the semiconductor crystal, in addition, a parasitic bipolar transistor, which constitutes the actual protection element. In the case of larger integrated circuits with a few 100 connection pins, these protective elements take up a significant part of the chip area: Because each connection pin has its own ggNMOS on the semiconductor chip with a structure size of approx. 800 µm. The size results from the fact that within the scope of the usual ESD simulation models , the discharge of the ggNMOS must not be permanently destroyed.
Individual evidence
- ↑ a b c Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev: ESD Protection Device and Circuit Design for Advanced CMOS Technologies . Springer Science & Business Media, 2008, ISBN 978-1-4020-8301-3 , Chapter 5.2.2: MOSFET-Based ESD Clamps, p. 122 ff .
- ↑ Yong-Seo Koo, Kwangsoo Kim, Shihong Park, Kwidong Kim, and Jong-Kee Kwon: Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On . tape 31 , no. 6 . ETRI Journal, December 2009, doi : 10.4218 / etrij.09.1209.0045 ( online ). Online ( Memento of the original from September 21, 2017 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.
