Latch-up effect

The technical term latch-up effect (from English "latching", also single event latchup , SEL ) describes the transition of a semiconductor component , such as in a CMOS stage, to a low-resistance state that can lead to an electrical short circuit . If protective measures are not taken, the latch-up effect leads to thermal destruction of the component.

A latch-up effect can be triggered by a short electrical voltage spike, for example by overvoltage or an electrostatic discharge . In addition, alpha or neutron radiation can also trigger a latch-up effect. Because of the (significantly higher) particle radiation in space, it is therefore not possible to use some highly miniaturized components in space.

root cause

Cross-section through the structure of a CMOS inverter and illustration of the parasitic thyristor

The layer structure of the individual dopings of n- and p-channel field effect transistors in a common substrate in an integrated circuit results in unwanted parasitic npn and pnp bipolar transistors . In terms of their mutual interconnection, these correspond to a thyristor , as shown in the graphic below using the example of an inverter in CMOS technology. The latch-up effect describes the ignition (switching on) of this parasitic thyristor. This short-circuits the supply voltage in the component. The current flowing is then high enough to create a thermal overload in that area and damage or destroy the circuit.

technical description

The critical geometric structure consists of a parasitic lateral npn and a vertical pnp transistor. The source-drain regions of the p-channel transistor are the emitter and the n-well is the base of the resulting pnp transistor, while the p-conducting substrate is the collector. The emitter, base and collector of the npn bipolar transistor correspondingly form the source-drain regions of the n-channel field effect transistors, the p-substrate and the n-well.

Both bipolar transistors are blocked under normal operating conditions. However, if high lateral currents flow through the tub and substrate due to external conditions (for example due to overvoltage at one of the inputs of a CMOS circuit, which are diverted into the substrate via protective diodes - not shown here), voltage drops occur at these points. These voltages polarize the base-emitter diode of one of the two parasitic transistors in the forward direction. There is a flow of current. The resulting collector current creates a voltage drop in the base parallel resistance ( R _p or R _n ) of the resulting complementary transistor. If the base-emitter voltage is exceeded here too, both transistors are now conducting. The consequences are positive feedback between the two parasitic bipolar transistors and a permanent low-resistance connection between the supply voltage and ground. This low-resistance connection can then only be separated by removing the supply voltage.

If the current gain of one of the two transistors is high enough, the arrangement remains in the active state (hold or latch-up state) even after the injected currents have disappeared. This leads to a malfunction of the component because the outputs are at a fixed level and no longer react to changes in the input. The flowing current is also only determined by the resistances of the track and the resistances of the base-collector paths of the transistors involved. The feeding metal tracks are usually not designed for this, and thermal destruction or fusion with underlying structures can occur.

Trigger mechanisms

The supply voltage exceeds the absolute maximum ratings (engl. Absolute maximum ratings ) of the block. A short voltage spike such as an electrostatic discharge can suffice here.
The voltage at the input or output connection exceeds the supply voltage by more than the voltage drop of a diode. This can happen due to voltage spikes on a signal line, e.g. B. by crosstalk .
Wrong or insufficient sequence in which different supply voltages are switched on in a circuit ( power up sequencing ). Circuit parts that have not yet been supplied, but to which signals from circuit parts that have already been supplied, can go into the latch-up state.
Another cause, which is rare under normal circumstances, is ionizing radiation , such as alpha or neutron radiation . The latch-up effect leads to failures of the electronics when unprotected CMOS circuits are operated in the vicinity of (strong) radioactive radiation sources. In this case, too, a single event can suffice.

Countermeasures

Structural countermeasures in semiconductors

In order to effectively suppress the triggering mechanisms described above, the following measures can be taken:

Large distances between the source-drain regions and the tub edges
Low-resistance substrate and p ⁺ -Schutzring (engl. Guardring ) next to the n ⁺ -type well
Low-resistance n ⁺ protection ring for the supply voltage connection
Isolation of the individual FETs by SOI substrates

The following problems arise. No low-resistance tub areas can be implanted on a highly doped material (low electrical resistance). This is why epitaxially coated wafers are used , which have a thin, high-resistance (low-doped) silicon layer on the highly doped material. The epi-layer accommodates well and transistor areas and the highly conductive substrate underneath then ensures effective latch-up protection. The only disadvantage of this process is the high cost due to the additional coating process.

Further measures are more of a structural nature and concern short connections to lines with high currents and the guard ring structures already mentioned in the list. These guard rings are highly doped p ⁺ -doped structures in the p-substrate and n ⁺ -doped structures in the n-well. They collect injected charge carriers and withdraw them from the lateral current. Guard rings are very space-consuming to implement, but are used for critical input and output circuits in CMOS technology.

Modern CMOS circuits have special geometric arrangements of the doping areas of the n- and p-FETs to suppress this interference effect at the inputs. In the aerospace and protective circuits (rapid current limiter) are used. Another disturbance caused by space radiation, the so-called SEU ( Single Event Upset ), does not destroy the circuit, but only to a temporary disturbance - depending on the circuit, even to the point of blocking, but this can be remedied by switching off / on. Both effects, SEL and SEU, are also known as single event effects , since they can be triggered by a single high-energy particle.

Countermeasures in the surrounding circuit

Countermeasures can also be taken outside the semiconductor module. In general, these are measures that ensure that the absolute limit data of the block are not violated:

Maintaining a switch-on and switch-off sequence for the operating voltages of components coupled to one another (power sequencing) so that no impermissible voltage differences occur between component connections.
If there are two supply voltages for the component, a Schottky diode between the supplies can ensure that they only differ by the voltage drop of the diode.
External protective resistors can be connected upstream of the inputs to prevent the input current from reaching the value for a latch-up
Protect the assembly and component connections from transients (caused by ESD or switching processes) with varistors or suppressor diodes
Current limitation of the supply (e.g. by a series resistor). Although this does not prevent the latch-up, it prevents thermal destruction of the component.

The disadvantage of these measures is that the additional components cause higher costs. The limited space on a circuit board can also limit the use of these measures.

Standards

JESD 78A ( IC Latch-Up Test ): Published by JEDEC . This standard defines a method to test the latch-up strength of an integrated circuit. It also defines classes and levels with which the latch-up resistance of a component can be specified in a comparable manner.