ARM Cortex-M3
The Cortex-M3 is a model from the ARM Cortex-M family ( ARMv7-M ) for microprocessors from ARM . The ARMv7 architecture was introduced in 2004 and can be seen as the successor to the ARMv6 architecture in the field of microcontrollers .
background
ARM architectures have become more and more complex over time. The first popular ARM processor was (and still is) the ARM7, followed by the ARM9 and ARM11 in various designs.
The areas of application for these three processor families can be roughly divided as follows:
ARM7: This was a sure-fire success in the field of microcontrollers. Originally not intended for use in microcontrollers, this processor has established itself there. ARM7-based microcontrollers are used where a little more computing power is required than e.g. B. can provide an 8-bit processor .
ARM9: Offers far more computing power than ARM7 and may be. a. used in real-time systems. Mechanisms such as B. MMU and MPU are used.
ARM11: High-end applications in the area of embedded systems that require a lot of computing power.
ARM divided its new architecture into three branches in order to create successors for all three areas. This division should enable an even broader use of the new architecture (s) in the world of embedded systems.
Cortex A: Application (operating system based applications)
Cortex R: Realtime (realtime applications)
Cortex M: microcontroller (cores for microcontrollers)
The Cortex-M3 architecture can thus be regarded as the successor to the ARM7 and provides more computing power than an ARM7 with a lower complexity of the programming model and a smaller chip area. Other subgroups, such as B. the M1, are z. B. available for implementation on an FPGA .
Basic structure
The design of the Cortex-M3 architecture developed by ARM is aimed at the application area of the (classic) 8- and 16-bit microcontrollers with a more powerful processor that is less complex in terms of the programming model. Like all previous ARM architectures, the M3 also has a 32-bit architecture internally, but works exclusively with the new Thumb2 instruction set. (Other ARM cores can switch between ARM and Thumb command sets.)
The heart of the Cortex-M3 processor is the Cortex-M3 core with a three-stage pipeline , based on the Harvard architecture . So there are two separate bus systems (and two separate memories) for loading data and commands, i. H. the processor can simultaneously read data and commands (or write data back to memory). Outwardly (programming model), however, the Cortex-M3 is a Von Neumann model , which means that its entire (shared) address space can be programmed linearly.
With a 32-bit processor, the available address space with 2 32 addresses for a microcontroller is huge. Therefore, both memories can be addressed in a common address space. This makes programming easier, since data that are stored in the flash (program memory) (for example constants) can be addressed directly in linear fashion without additional effort.
Some new features have been integrated into the core of the Cortex-M3. This includes a real nested vectored interrupt controller, a kind of jump prediction and multiplication in just one cycle.
Jump prediction
Only 16 bits are required to load a command, but the memory interface is 32 bits wide and two commands are always loaded simultaneously ( fetch ). One command is cached in each case. In the event of a jump, it is only known in the Exec stage (see pipelines) whether the jump should be carried out or not. If not, work continues as usual. If so, the buffered instruction is loaded into the pipeline and processed with it. Thus, only one clock (instead of two) is lost in the three-stage pipeline.
Thumb2
The processor core works exclusively with the new Thumb2 instruction set, which means that it works a lot more efficiently than older ARM processors with Thumb (in terms of execution time) and operates with around 30% more compact code than older ARM processors in ARM mode. The Thumb2 instruction set comprises both 16- and 32-bit instructions, which are designed to work as efficiently as possible with compilers, i. e.g. to implement C / C ++ code, but can of course also be used in assembler.
Almost all classic ARM commands (like Thumb) are only 16 bits long. This enables two commands to be loaded in just one cycle.
Other major innovations in Thumb2 include: B. native bitfield manipulation , hardware division and if-then instructions. The latter allow conditional execution of code (without jumps).
Programming model kept simple
Programming simple tasks does not require precise knowledge of the internal structure and structure of the kernel, nor does it require any knowledge of assemblies for programming. The programming of interrupt handlers is made easier by the hardware-based interrupt scheme.
Periphery
The Cortex-M3 already has some peripherals. So are z. B. a real vectored interrupt controller (VIC), memory protection, timer and debug and trace options integrated in the processor.
Additional peripherals, such as UART , additional timers, PWM , I2C , SPI , etc., are developed by the chip manufacturers or purchased from ARM as IP (Intellectual Property). These can - as usual - be addressed via registers.
Vectored interrupt controller
With the implementation of the NVIC, the Cortex-M3 uses a real vector table, i. H. there are jump addresses (vectors) instead of the complete commands previously common with ARM-based controllers. These vectors (addresses) can be loaded and jumped to very quickly via its direct interface to the core.
The interrupt controller of the Cortex-M3 is very closely connected to the core. The processor automatically saves the context. Other special features such as "Late Arriving Interrupt" and "Tail Chaining", in which a POP / PUSH sequence is saved (see ARM7), result in a very efficient interrupt system. In general, each interrupt can be assigned a priority, i. H. the priority is not fixed by the position in the vector table. The priorities can be organized in groups. Interrupts in different groups can interrupt each other; within a group, an interrupt of a higher priority does not interrupt a lower priority. This is important to avoid deadlocks with shared hardware.
Register set
Classic ARM cores have a set of over 37 32-bit registers that are divided into different modes. Different registers are visible depending on the mode. This saves the need to save registers e.g. B. for the FIQ (shadow registers R8 to R14 cover the registers from the user mode).
The Cortex-M3 only has one set of registers (R0 to R12, SP, LR, PC and CPSR) and an additional stack pointer (SP). When jumping to an ISR, the core automatically saves the eight registers PC, CPSR, LR R0 to R3 and R12.
silicon
ARM is a fabless company, so it does not manufacture any chips itself, but develops processor architectures (including peripherals) and licenses them to other companies.
The startup Luminary Micro made the first implementation of Cortex-M3 in a microcontroller. Luminary Micro is also a fabless company and manufacturer of the "Stellaris" family of microcontrollers (LM3S811, LM3S828, and others). A variety of peripherals were implemented on the chip; in addition to the common elements such as UART, timer, etc. B. a complex 3-phase motor control.
The STM32 family from STMicroelectronics is also based on the Cortex-M3 core from ARM and includes many peripheral elements, for example for 3-phase motor control, Hall or incremental encoder interface, DMA, 12-bit ADC, and a few more Standard peripherals. Aspects of this implementation are e.g. B. the debug module, which is separate from the core, which enables access to the core even if the clock tree is incorrectly programmed, and a clock security circuit that detects and activates a failure of the external clock (e.g. the crystal) can switch an internal oscillator - without the core "crashing". A clean programming model for the peripherals and a system of header files for register mapping, which enables simple programming of the core even without a driver library, round off this microcontroller.
ARM Cortex Microcontroller Software Interface Standard (CMSIS)
In order to enable a common basis for programming Cortex-M-based microcontrollers, ARM published a standard HAL on November 12, 2008 . It was created in cooperation with partners from industry and offers a common, easy-to-use programming basis on Layer 1, the abstraction of the registers and their mapping to the memory layout. So far, there have been separate approaches to the programming model for the multitude of implementations, from #defines on individual registers to complex structures. The HAL uses the concept of complex structures, whereby a structure exists for each peripheral, which completely maps the registers of the respective peripheral. The structures are mapped to the addresses of the peripherals, which enables access to Peripheral → Register = Value or value = Peripheral → Register .
Layer 2, a very efficient layer of inline functions, offers additional helper functions for simple NVIC handling as well as a SystemTick timer setup that is tailored to the needs of real-time operating systems .
Web links
Individual evidence
- ↑ Cortex-M3 Processor (english) , Cortex-M Series at arm.com, accessed on July 24, 2014
- ↑ "The Thumb-2 instruction set" , p. 15, ARM (PDF file; 5.2 MB)