Flash memory controller

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The flash memory controller is part of a digital storage medium (e.g. SD card , CompactFlash , USB mass storage device and solid state disks (SSD)) that controls communication between flash memory and computer as well as certain other processes. The controller manages where and how the data is stored in the physical memory cells and has an important influence on the performance and service life of the flash memory. The flash memory controller is also responsible for wear leveling , error correction (ECC) and mapping ( flash translation layer ).

Flash memory controller in a USB mass storage device. The flash memory chip is located on the back of the circuit board

Read, write, delete

Flash memories consist of data blocks and pages . Blocks are formed from multiple pages and one page is formed from multiple memory cells. The flash memories can only be deleted in blocks and written to page by page. The file systems use certain access patterns to read from and write to a memory. The smallest unit for read access is usually a sector with 512 bytes .

However, since only individual pages can be written on, this page must be physically empty. If this is not the case, the content of the page must first be deleted, which is only possible if you delete the entire block and thus all pages on the block.

Write amplification

Usually, more data physically has to be written to the flash memory than has to be sent from the computer or file system . Write amplification provides information about the effectiveness with which data is written from the host to the flash memory. In order to be able to assess this better, there is a Write Amplification Factor (WAF), which specifies the amount of information that must also be written to a flash memory together with a certain amount of user data.

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Example: With a WAF of 4, with random write processes of 4  KB , 16 KB are actually written to the flash memory.

This means that the physical amount that is actually written to the flash memory exceeds the logical amount. This is due, on the one hand, to the requirement for block-wise deletion and page-by-page writing, and on the other hand, because mapping and other algorithms also write information and logging data to the flash memory.

Calculating the WAF depends on many different factors (for example, the data access / write pattern, the mapping granularity or the flash technology ( SLC / MLC / TLC )). However, this can increase efficiency while reducing the write and erase cycles. In this way the service life of a flash memory can be extended considerably. NAND flash memories wear out physically through write and erase cycles, which means that data can no longer be reliably stored after a certain period of use.

Error correction procedure (ECC)

Since some memory cells can have an incorrect state due to wear, production variances and other physical effects and therefore occasionally deliver incorrect bits when reading back ( raw bit error rate ), the flash memory controller usually also includes an error correction unit. There are major differences in the algorithms used, as well as the strength and quality of the correction. Some algorithms deliver incorrect bit values ​​with a certain probability, while others can no longer correct them after a certain amount of errors and instead return the result “uncorrectable”. The strength of the correction capability of a controller is specified in bits or Kbytes.

Wear-leveling

The wear-leveling is one of the most important tasks handled by the flash memory controller. This function ensures that the memory cells on the flash memory are worn evenly in order to increase the life of the flash memory system as a whole. For this purpose, the data on the flash memory is permanently and evenly relocated. A distinction is made between dynamic and static wear leveling . The dynamic wear leveling selects the block that has been used the least so far from the set of currently free blocks for a new write access. A danger of dynamic wear leveling is that the cells of the remaining free blocks are quickly worn out in a heavily used flash memory system. Static wear leveling includes blocks that contain static data and relocates them to other blocks if necessary. In order to achieve the longest possible service life, both methods are usually used in SSDs.

Flash Translation Layer (FTL) and mapping

The Flash Translation Layer takes over the conversion ( mapping ) from logical to physical addresses. This means that the logical accesses from the host side are translated into physical accesses on the flash memory side. There are different mapping approaches depending on the required application.

  • The block-based mapping (block-based mapping) converts logical blocks into physical blocks. The pages or sectors within the blocks are mapped one-to-one from the host to flash.
  • With page-based mapping , logical pages are mapped onto physical pages, with the block numbers forming part of the page address. A logical page can therefore be placed on any page within any block.
  • The third mapping approach is sub-page-based mapping . Logical units that are smaller than one page are formed and then mapped onto physical units. The problem with this method is that the smallest writing unit is a page, which is why the controller combines these units into one page.

Garbage collection

The garbage collection ("garbage collection") has the task of generating free blocks . To do this, it is necessary to check not yet completely empty blocks on the flash memory and, if necessary, to free them by consolidating the valid data so that they can be deleted and then rewritten. This process is important for the performance of the flash memory, since a deletion process in the file system or from the host only declares files to be invalid, but they are not physically deleted. The actual data is retained in the memory cell. The garbage collection cleans up, so to speak. This process usually runs in the background to keep the impact on the storage speed low.

Individual evidence

  1. ↑ Nico Stamp: Everything you need to know about SSDs - What is the function of the controller and firmware? In: Computerwoche . October 6, 2014, accessed June 29, 2015 .
  2. ↑ Design & Electronics. Know-how for developers. Issue 1, 2015, pp. 18–22.
  3. ↑ Klaus Manhart: Under the SSD hood - Solid State Discs: The technology - Structure of flash memory: Pages and Blocks - TecChannel.de. In: tecchannel.de. March 11, 2014, accessed June 28, 2015 .
  4. ↑ Corinna Puhlmann: SSDs: Read the data sheet correctly. In: elektroniknet.de. May 18, 2011, accessed June 28, 2015 .
  5. ↑ a b Susan Heidirch: New flash management architecture enables MLC for industrial storage. (PDF) In: BAS + ECE. February 2015, accessed June 29, 2015 .
  6. ↑ ECC - Error Correcting Code. In: elektronik-kompendium.de. June 25, 2008, accessed June 28, 2015 .
  7. ↑ Corinna Puhlmann: Safer than the conventional hard drive! In: elektroniknet.de. May 16, 2011, accessed June 28, 2015 .
  8. ↑ How does an SSD work? About life cycles, wear leveling, garbage collection and the trim command. - tiramigoof. In: tiramigoof.de. November 15, 2014, accessed June 28, 2015 .
  9. ↑ Tae-Sun Chung, Dong-Joo Park, Sangwon Park, Dong-Ho Lee, Sang-Won Lee, Ha-Joo Song: A survey of Flash Translation Layer . In: Journal of Systems Architecture . tape 55 , no. 5-6 , May 2009, pp. 332–343 , doi : 10.1016 / j.sysarc.2009.03.005 ( PDF [accessed June 28, 2015]).
  10. ↑ elektroniknet.de Corinna Puhlmann, May 16, 2011.
  11. ↑ Nico Stamp: Everything You Need to Know About SSDs - What Is Garbage Collection? In: Computerwoche. October 6, 2014, accessed June 29, 2015 .