Silicon gate technology

from Wikipedia, the free encyclopedia

The silicon gate technology (SGT), also called silicon gate process (English silicon gate (MOS) technology / process ), is a production variant for integrated circuits (ICs) based on field effect transistors with an insulated gate electrode ( IGFET ), in which the gate electrode is made of highly doped polycrystalline silicon ( polysilicon , poly-Si) instead of the aluminum that was customary at the time. Including further developments (especially CMOS technology ), silicon gate technology is the dominant manufacturing technology for microelectronic products . In the field of high - performance processors , however, it was replaced in the mid-2000s by the high-k + metal gate technology , which again uses a metallic gate electrode . The principle of silicon gate technology is still widespread and is used for products up to 28 nm technology nodes .

Process sequence

The silicon gate process is a planar process , which means that all processes are carried out from the surface and the functional components are located just below the surface. It was originally introduced for the manufacture of integrated circuits on p-channel insulated film field effect transistors (p-channel IGFET), sometimes also referred to as the PMOS process . In the first process stage an n-doped silicon is single crystal - wafer is thermally oxidized to produce a well 2 microns thick "field oxide" for the isolation of the components. Then the active area (where the transistors will later be located) is photolithographically masked and the field oxide in this area is removed so that the silicon is uncoated again. In the second process stage, thermal oxidation follows under controlled conditions in order to initially produce the later, significantly thinner gate oxide (then approx. 100 nm) in the entire active area. This is followed by the full-area deposition of polysilicon, for example by chemical vapor deposition (CVD). In the third section, the polysilicon layer is photolithographically masked and then locally removed in order to define the gate regions. This is followed by the production of the source / drain areas by ion implantation of boron. In contrast to the process with a gate electrode made of aluminum (see Metallic Gate Electrode # Process sequence of the "aluminum gate technology" (1960s ) ) No further mask step necessary, since these areas were already defined and opened during the gate structuring. In the case of maskless ion implantation, the doping atoms remain stuck above the electrically inactive areas in the field oxide, so that they remain electrically ineffective here. A desired doping of the gate electrode made of polysilicon with boron also takes place. The p-doping leads to a lower sheet resistance and the desired change in the work function. In the last stage of the process, a thick layer of silicon dioxide or nitride is deposited. This is again structured photolithographically and the areas of the source, drain and gate contacts are opened. Finally, aluminum is deposited and structured in order to produce the contact and first metallization level .

Advantages and disadvantages

By replacing the metal gate electrode by a doped polysilicon is the difference in work function between the gate electrode and the underlying semiconductor of the channel is no longer fixed, but can be adjusted of the silicon gate by the doping. For p-channel components (on <100> silicon) , for example, this allowed the threshold voltage to be reduced from 2.7 V (aluminum) to 1.6 V (polysilicon) with a constant dielectric thickness of approx. 100 nm.

By using the polysilicon electrode as a masking for the transistor channel and the whole-area doping, the source and drain regions are defined without any further photomask, which is why we speak of “self-adjusting / aligning” in this context. This completely eliminated the overlay offset of up to 0.2 µm between the gate and the source / drain regions, which is unavoidable with aluminum gate technology . With the significantly improved alignment and the negligible lateral diffusion of the dopants under the gate during the necessary annealing step, the gate-drain capacitance is significantly reduced (to a negligibly small value for the circumstances at the time). Furthermore, the silicon gate technology required the same number of (four) photolithography steps as the aluminum gate technology common at the time. Due to the separation of the gate structuring and the contacting as well as the lower capacitance, however, noticeably higher component densities (factor 1.5) could be achieved. All in all, it resulted in a lower space requirement, an improved production yield and an increase in switching speed (approx. Factor 3 by reducing all parasitic capacitances by approx. 10%).

Another advantage of gate electrodes made of silicon compared to aluminum is the significantly higher thermal budget for subsequent processes, such as healing processes after ion implantation / diffusion. This enabled the order of diffusion and application of the gate electrode to be reversed. This is made possible by the much higher melting temperature of polysilicon compared to aluminum ( T s, Al = 660.2 ° C), as well as the better protection of the gate dielectric by the gate and the protective oxide. At the same time, it increases the compatibility with the then usual manufacturing process for bipolar transistors, which could now be more easily manufactured on a chip together with IGFETs.

Areas of application and meaning

The principle of using polysilicon as a gate material was first published in an article by Bell Labs employees Robert Kerwin , Donald Klein and John Sarace in 1968, but a patent was applied for in 1967. In 1968, Fairchild employees Federico Faggin and Thomas Klein developed a manufacturing process from this and demonstrated the first integrated circuit using p-channel silicon gate technology, the Fairchild 3708 (a redesign of an existing analog 8-channel multiplexer in p-channel -Aluminium gate technology, Fairchild 3705 ).

Faggin's concept was adopted by Intel as the primary technology for semiconductor memory components. The first commercial products in silicon gate technology were SRAM ( Intel 1101 , 1969) and DRAM components ( Intel 1103 , 1970) in PMOS technology from Intel. The first microprocessor ever followed in 1971, the Intel 4004 . However, PMOS had significant limitations in switching speed, which is why Intel developed NMOS silicon gate technology a few years later . The first product of this kind was Intel's 8080 (1974). This was followed by HMOS silicon gate technology (HMOS = high-performance MOS ), which, together with projection exposure, enabled a further increase in the integration density and more powerful components. Another step followed in 1985, the advanced CMOS process , a further development of the CMOS technology developed by the RCA in the 1950s, used in Intel's 80386 . The advantage of CMOS is a significantly lower power consumption compared to PMOS and NMOS by using p-channel and n-channel field effect transistors. However, it has the disadvantage that it requires more than one diffusion step and a little more area. The manufacture of such circuits for VLSI applications became possible at a reasonable price with the CMOS silicon gate process.

From today's perspective, silicon gate technology and its further developments (especially CMOS technology ) have been the dominant manufacturing technology for the manufacture of semiconductor memories and integrated circuits since their invention in the 1970s up to the 28-nm technology node . It was not until the introduction of the 32-nm technology node in the mid-2000s that polysilicon was replaced as the gate material for high - performance processors . The new high-k + metal gate technology again uses a metallic gate electrode as well as special dielectrics and is characterized, among other things, by a significantly lower power loss of the processors. The self-adjusting principle introduced with silicon gate technology for defining the source / drain areas without a photolithography step is still used here.

annotation

The best-known representative of insulated-gate field-effect transistors (IGFET) is the MOS field-effect transistor. Its name is derived from the typical layer sequence of the transistor, that is, a metallic gate electrode (mostly aluminum) that is separated from the semiconducting channel region (silicon) by an electrically insulating oxide (silicon dioxide). Hence the German-language name metal-oxide-semiconductor field-effect transistor (MOS-FET). This was the common design for planar field effect transistors in the mid-1960s. With the introduction and spread of silicon gate technology, this designation was retained, even if it no longer corresponded to the actual structure. This is why silicon gate technology is also referred to as MOS technology / process.

Individual evidence

  1. ^ Hans-Günther Wagemann, Tim Schönauer: Silicon planar technology: basic processes, physics and components . Springer-Verlag, 2013, ISBN 978-3-322-80070-1 .
  2. ↑ a b c Federico Faggin, Thomas Klein: A Faster Generation Of MOS Devices With Low Thresholds Is Riding The Crest Of The New Wave, Silicon-Gate IC’s . In: Electronics . tape 42 , no. 20 , 1969, p. 88 ( facsimile [accessed August 1, 2015]).
  3. ↑ JC Sarace, RE Kerwin, DL Klein, R. Edwards: Metal-nitride-oxide-silicon field-effect transistors, with self-aligned gates . In: Solid-State Electronics . tape 11 , no. 7 , 1968, p. 653-660 , doi : 10.1016 / 0038-1101 (68) 90067-1 .
  4. ↑ Patent US3475234 : Method for making MIS structures. Filed March 27, 1967 , published October 28, 1969 , inventors: Robert E. Kerwin, Donald L. Klein, John C. Sarace. ‌
  5. ^ F. Faggin, T. Klein, L. Vadasz: Insulated gate field effect transistor integrated circuits with silicon gates . In: Electron Devices Meeting, 1968 International . tape 14 , 1968, p. 22–22 , doi : 10.1109 / IEDM.1968.187948 ( facsimile [accessed August 1, 2015] abstract of the conference contribution).
  6. ^ F. Faggin, T. Klein: Silicon gate technology . In: Solid-State Electronics . tape 13 , no. 8 , 1970, pp. 1125-1144 , doi : 10.1016 / 0038-1101 (70) 90124-3 .