High-k + metal gate technology

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Schematic cross-section through the gate structure of a transistor in high-k + metal gate technology

The high-k + metal gate technology (HKMG technology) referred to in the semiconductor technology, a specific structure of metal-insulator-semiconductor field effect transistors (MISFETs) of modern integrated circuits (IC). The technique is characterized by the use of materials with a higher relative permittivity as silicon dioxide , so-called high-k materials , as an insulating layer and a metallic gate electrode ( metal gate ).

background

The constant scaling of microelectronic components since the late 1970s meant that the structure width was reduced from several micrometers to just 90 nm in 2003. The scaling was necessary to increase the integration density (number of components per area) of ICs.

This scaling reached its limits in the mid-2000s. Because with the scaling of the structure width, a scaling of all other components of the MISFET is also connected. Since the 1960s, amorphous silicon dioxide, which was produced by thermal oxidation of the silicon substrate , has been used as an insulation layer between the semiconducting channel region and the gate electrode. The thickness of the insulation layer was only a few atomic layers in the 2000s (approx. 1–2 nm). With these layer thicknesses, the influence of tunnel effects and minimal manufacturing tolerances increases significantly, so that tunnel currents that occur through the insulation layer have a significant share in the power loss of the ICs.

Since the thickness is not further reduced in the 65 nm manufacturing process introduced by Intel in 2005 for the reasons mentioned above, alternative materials for the silicon dioxide (SiO 2 ) insulation layer had already been sought. The solution lay in the introduction of so-called high-k dielectrics, which allow higher layer thicknesses and thus lower tunnel currents with the same electrical properties (the electrical capacitance of the MISFET in particular is important here) (see reasons for using high-k dielectrics ).

When testing electrical components with high-k dielectrics and a polysilicon gate, further negative effects occurred. These include, above all, an increase in the threshold voltage compared to theoretical assumptions and a reduced charge carrier mobility. The so-called Fermi-level pinning causes the real threshold voltages to be higher than they should theoretically be due to the doping of the channel area and the thickness of the insulation layer. This effect is by adjusting the work function by means of additional metal layers at the interface of the gate electrode to the high-k material compensated. However, each transistor type (p-channel and n-channel transistors) requires its own adaptation, which increases the complexity even further. This applies above all to the use of bulk silicon substrates; this problem is less pronounced with silicon-on-insulator substrates. Another problem is the fact that the work function of the metal should correspond as closely as possible to that of highly doped silicon. Extensive studies have shown, however, that there is no exactly matching metal and that the work function of metals has to be adjusted, for example by doping .

Furthermore, a reduced charge carrier mobility was observed in transistors . This is caused by the oscillating dipoles in the high-k material, which lead to oscillations in the crystal lattice of the semiconductor (so-called phonons ). The phonons in turn scatter the charge carriers in the area of ​​the channel area near the interface and slow them down. The consequence is a reduced switching speed of the transistor. As it turned out, the charge carrier density in the gate electrode (at the interface with the dielectric) influences this effect. Since metals have a charge carrier density that is at least two orders of magnitude higher than silicon, the use of a metallic gate represents a significant improvement.

With the introduction of HKMG technology at the 45 nm technology node in 2007, Intel was the first company to use HKMG technology in commercial products. At that time, a hafnium (IV) oxide- based material was used as the high-k material, and production was based on the so-called gate-load principle (see below). With the reintroduction of a metallic gate electrode, the effect of charge carrier depletion within the polysilicon gate was circumvented. It represented an increasing challenge in IC production. This turned the polysilicon-silicon dioxide field effect transistor, which had been strictly speaking no longer a MISFET or MOSFET, into a metal-oxide-semiconductor field effect transistor (MOSFET). . Overall, the use of HKMG led to the introduction of numerous new materials and chemical substances in the manufacturing process.

Manufacturing techniques

The term HKMG only describes the layer stack that is present after production and does not make any statements about the materials used. Furthermore, the complex structure of the transistor allows variations in terms of the manufacturing processes used and their sequence. The HKMG technology is therefore divided into three main manufacturing strategies:

  • gate first ; also called metal inserted poly-silicon , MIPS
  • gate last ; Also replacement metal gate , RMG, replacement gate , RG, or damascene gate , called
  • fully silicided gate (FUSI, dt. 'fully siliconized gate')

The first (English for 'first') and last (English for 'last') refer to whether the metallic gate electrode was created before ( first ) or after ( last ) the activation of the source and drain regions becomes. Activation is a high-temperature process that aims to integrate the doping atoms introduced by ion implantation into the crystal lattice .

Gate-first process

In the gate-first process, the metallic gate electrode is produced before the implantation and activation of the source and drain regions. This includes the deposition of the high-k dielectric and the gate electrode (possibly with the additional layers for adapting the work function). Finally, a sacrificial layer made of polysilicon is usually applied that protects the gate stack from the subsequent implantation of the source and drain regions.

The main advantage of the gate-first approach is that the process sequence essentially corresponds to that of a polysilicon gate, which means that fewer adjustments to the manufacturing process are necessary.

Gate load process

Schematic cross-sections through an n-channel and a p-channel MOSFET in high-k + metal gate technology (in replacement metal gate technology) as introduced by Intel in 2007 with the Penryn processors in 45 nm technology .

In the gate-load process, the metallic gate electrode is only produced after the implantation and activation of the source and drain regions. Optionally, the high-k layer can only be applied after the implantation.

The most common method for this is the so-called replacement metal gate technology (RMG). For this purpose, a conventional polysilicon gate is first produced and the source and drain regions are implanted / activated. The polysilicon of the gate electrode is now selectively removed, a kind of sacrificial layer (often called a dummy gate in English). If no high-k material has initially been deposited as a dielectric, this is also etched selectively. Then the now “empty” gate is filled with the desired layer stack (high-k dielectrics, matching metals and gate electrode).

The advantage of the gate-load approach is the lower thermal load on the high-k material and the metal layers, because the high-temperature steps for activating the doping regions were carried out beforehand.

The disadvantage is the increased effort in production, for example the gate electrode must be “opened” before the polysilicon is etched. This can be made possible, for example, by chemical mechanical polishing (CMP). The high levels of accuracy and the different materials make the process very demanding. This is because a gate that is not fully open hinders the etching and an overpolished gate can negatively affect the electrical properties of the transistor. In addition, all transistors on the wafer with a diameter of up to 300 mm must be opened as similarly as possible.

Fully-Silicided-Gate-Process

The fully silicided gate process is essentially a continuation of the polysilicon gate technology. Here, silicides are used for better electrical contacting of the gate electrode (the process is also known as polycide ). These are produced by depositing a thin layer of a metal, for example nickel, on the polysilicon layer. In a high-temperature process, the metal atoms diffuse into the polysilicon and form very good electrically conductive silicide at the interface - earlier titanium and cobalt disilicide and now often nickel disilicide - and with a low contact resistance to the metallic contacts (mostly made of tungsten ). As mentioned, this idea is continued in the fully silicided gate process and the entire polysilicon is converted into a silicide or replaced (comparable to the replacement metal gate technique). This solves the gate depletion problem. Strictly speaking, it's not really a metal gate technique. With the polysilicon gate technology, the silicide production is usually combined with the silicide formation for the source and drain contacts. However, too thick a silicide layer in these areas can have negative effects on the properties of the transistors. To prevent this, processes have also been proposed in which the two silicide formations are separated. The source and drain regions must be protected by a cover layer from silicide formation in the gate.

The disadvantage is the limited possibility of adapting the work function of the silicides, which is why this method has not yet been able to establish itself.

Construction variants and materials

In addition to the manufacturing variants, there are also different variants for building the gate stack, for example:

  • a metal layer and a dielectric layer ( single metal, single dielectric , SMSD): The simplest structure, where the dielectric and then the metallic gate are deposited separately for p-channel and n-channel FETs.
  • a metal layer and two dielectric layers ( single metal, dual dielectric , SMDD): Similar to SMSD, only the dielectric consists of two layers. This is done above all for an improved interface with lower interface charges or for an improvement in layer adhesion.
  • Two metal layers and a dielectric layer ( dual metal, single dielectric , DMSD): Similar to SMSD, only a further metal layer is deposited between the dielectric and the actual metal gate to adjust the work function.
  • two metal layers and two dielectric layers (English dual metal, dual dielectric , DMDD): A combination of SMDD and DMSD.

Theoretically, this scheme can be continued as desired, but the complexity and thus the manufacturing effort increases very sharply.

Typical materials for the gate electrode (not in the fully silicided gate process) are currently titanium nitride (TiN, for PMOS) or titanium aluminum nitride (TiAlN, for NMOS). Various materials are used to adjust the work function, especially doped hafnium oxide, aluminum oxide (Al 2 O 3 ) and lanthanum oxide (LaO).

Advantages and disadvantages

The main advantages of HKMG are the drastic reduction of the gate leakage current and the associated possibility of further scaling microelectronic circuits; In the case of the 45 nm technology from Intel, this was a scaling of the transistor dielectric by a factor of 0.7 and a reduction of the gate leakage current by a factor of 1000 for PMOS or 25 for NMOS. This is associated with a lower supply voltage and thus enables faster and more energy-efficient transistors to be produced. The HKMG technology makes current top products (2011) with a structure width in the range of 28 nm and smaller possible. HKMG processors with the same design could be operated with a higher clock frequency than conventionally manufactured processors. In practice, however, such a transfer of a processor design to a completely new manufacturing process is not carried out. Rather, new elements are introduced in the processor architecture with each technology level and thus with higher integration density.

Compared to the previously used polysilicon-silicon dioxide structure, the manufacturing costs are much higher. HKMG technology not only increased the number of necessary process steps, but also made higher demands on the manufacturing technology and completely new processes had to be introduced. One example is the production of high-k layers: at the beginning of the research work, high-k layers were produced using conventional chemical and physical vapor deposition coating processes. This enabled very good, smooth and sufficiently thin layers to be produced. The electrical properties of high-k capacitors and transistors produced in this way were, however, rather poor. The cause of the problem was charges at the interface between the silicon substrate and the high-k layer. These interfacial charges arise from atomic defects or open bonds. They trap charge carriers and change, for example, the voltage that has to be applied to reach the threshold voltage of the transistor. Similar problems were encountered with silicon dioxide as early as the 1960s. At that time the problems with the introduction of the thermal oxidation of silicon for the production of the oxide layer were solved. However, there is no comparable coating process for high-k materials. The solution this time was the introduction of a coating process that allows the production of atomically smooth layers on the (also atomically smooth) silicon substrate, atomic layer deposition (ALD).

literature

  • Mark T. Bohr, Robert S. Chau, Tahir Ghani, Kaizad Mistry: The high-k solution . In: IEEE Spectrum . tape 44 , no. 10 , 2007, p. 29–35 , doi : 10.1109 / MSPEC.2007.4337663 ( HTML - With clear representations of the problems to be solved).
  • R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, M. Metz: High-κ / metal-gate stack and its MOSFET characteristics . In: Electron Device Letters, IEEE . tape 25 , no. 6 , 2004, p. 408-410 , doi : 10.1109 / LED.2004.828570 .

Web links

Individual evidence

  1. ^ Howard R. Huff: High dielectric constant materials: VLSI MOSFET Applications . Springer, 2005, ISBN 978-3-540-21081-8 , pp. 457 f .
  2. ↑ a b Mark T. Bohr, Robert S. Chau, Tahir Ghani, Kaizad Mistry: The high-k solution . In: IEEE Spectrum . tape 44 , no. 10 , 2007, p. 29-35 , doi : 10.1109 / MSPEC.2007.4337663 .
  3. ↑ a b K. Mistry et al .: A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging . In: Electron Devices Meeting, 2007. IEDM 2007. IEEE International . IEEE, 2007, ISBN 978-1-4244-1507-6 , pp. 247-250 , doi : 10.1109 / IEDM.2007.4418914 . Quoted in C. Auth et al: 45nm high-k + metal gate strain-enhanced transistors . In: Intel Technology Journal . Vol. 12, No. 2 , 2008, p. 77–86 , doi : 10.1109 / VLSIT.2008.4588589 ( PDF ( Memento of July 10, 2012 in the Internet Archive )).
  4. ↑ Balapradeep Gadamsetti: Intel's Low Power Technology - With High-K Dielectric. (No longer available online.) Archived from the original on July 15, 2016 ; Retrieved September 18, 2014 .
  5. ^ Howard R. Huff: High dielectric constant materials: VLSI MOSFET Applications . Springer, 2005, ISBN 978-3-540-21081-8 , pp. 456 .