Salicide process

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In semiconductor technology, the English term salicide refers to a process for producing electrical contacts between the active areas of the silicon substrate (source and drain of the MOSFET ) and the conductor track levels . The term itself is a hybrid of initial and formation of syllables, that is, an acronym of s eleven a ligned si licide (dt. Self-aligned silicide ), that is, a process in which without the aid of a separate photolithographic patterning ( "self-adjusting") a localized silicide is generated.

Analogous to the salicide process, the Polycide process refers to the formation of silicide in a polysilicon layer , for example to form the contact of the gate electrode. However, the use of the term is not always free of contradictions, so the simultaneous formation of silicides on the source and drain regions and the gate electrode of the MOSFET is also referred to as the salicide process.

Contact formation

The salicide process begins with the deposition of a so-called spacer made of silicon dioxide or silicon nitride on the side wall of the gate electrode, that is, between the gate and the source / drain regions. This is followed by cleaning the wafer, for example with organic solutions, in dilute hydrofluoric acid and deionized water , and then drying it with nitrogen . The cleaning is intended to ensure that the previously exposed silicon areas (Si) are free of impurities and oxide residues, since such impurities can have a greater influence on the resulting silicide phase.

A thin metal layer such as nickel (Ni), titanium (Ti), cobalt (Co) or platinum (Pt) is then deposited - mostly by sputter deposition. After deposition, followed by an initial high-temperature step - a so-called Rapid Thermal Processing (dt .: rapid thermal processing ) - at about 450-700 ° C (depending on the metal) in a nitrogen atmosphere. The metal atoms diffuse into the silicon or vice versa (depending on the metal), resulting in silicide formation. An important aspect of the salicide process is that the metal ions diffuse into the silicon but not into silicon dioxide and silicon nitride.

After the silicide formation, the unreacted metal is removed in an etching step. A silicide contact remains on the previously exposed silicon areas. Since this silicide generally does not have the desired electrical properties, that is to say has too high an electrical resistance, a second high-temperature step at slightly higher temperatures followed after the unreacted metal was removed. The existing silicide is converted into a silicide phase with lower electrical resistance , for example titanium disilicide phase C49-TiSi 2 in C54-TiSi 2 or cobalt silicide (CoSi) in cobalt disilicide (CoSi 2 ).

A manufacturing process that can be fully integrated into the CMOS manufacturing can be more complex, however, with additional temperature steps, surface treatments or etching processes.

Process requirements

As already mentioned, transition metals such as titanium, cobalt, nickel, platinum and tungsten are typically used as metal components of the silicide in the Salicde process or their application is being researched. A challenge in the development of a salicide process is the controlled formation of a desired silicide phase with low electrical resistance through a metal-silicon reaction, some of which are very complex. When cobalt reacts with silicon, for example, Co 2 Si, CoSi, CoSi 2 and other compounds can be formed. However, only CoSi 2 has a sufficiently low resistance to form an effective electrical contact. In the case of other compounds, the desired low-resistance phase is not thermodynamically stable, for example C49-TiSi 2 , which is metastable with respect to the C54-TiSi 2 phase with high electrical resistance. Among other things, this must be taken into account in subsequent processes so that an undesired phase change does not occur.

Another challenge for successful process integration is lateral growth, especially under the gate, which can short-circuit the transistor.

Individual evidence

  1. ↑ a b c L. J. Chen (Ed.): Silicide Technology for Integrated Circuits (Processing) . IET, 2004, ISBN 978-0-86341-352-0 , pp. 5, 18-19, 33-34 .
  2. ↑ a b Z. Ma, LH Allen: 3.3 Fundamental aspects of Ti / Si thin film reaction . In: LJ Chen (Ed.): Silicide Technology for Integrated Circuits (Processing) . IET, 2004, ISBN 978-0-86341-352-0 , pp. 50-61 .
  3. ↑ T. Kikkawa, K. Inoue, K. Imai: Chapter 4. Cobalt silicide technology . In: LJ Chen (Ed.): Silicide Technology for Integrated Circuits (Processing) . IET, 2004, ISBN 978-0-86341-352-0 , pp. 77-94 .