Logic synthesis
The logic synthesis is an area of technical computer science and electrical engineering / communications engineering that deals with the design of circuits busy, a Boolean function realized. The basis is Boolean algebra . The aim is to find the most cost-effective one from the many possibilities for realizing a Boolean function. For the implementation of Boolean functions by a PLA , cost-effective means to find a Boolean function with as few lines as possible (according to the monomials of the Boolean expression) and as few transistors as possible per line (according to the literals of the Boolean expression). This is achieved using the Quine and McCluskey method or the obsolete method of the Karnaugh-Veitch diagram .
For FPGAs , the task is more complex because the same function can be realized from different basic elements of the FPGA. For example, a 4 bit shift register can consist of:
- 4 flip flops or
- an SRL16 macro (16 bit shift register) or
- a SRAM block
will be realized.
If you grasp the function of the shift register in a more general way and use it for parallel-serial conversion, further implementation options are possible:
- Multiplexer with 2-bit counter
- Multiplier block
For an optimal solution, the logical equations around here are boundary conditions (Engl. Constraints ) supplement.
When developing digital integrated circuits , such as microprocessors , logic synthesis is one of several design steps.